Memorysystem architecture

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Chapter 6

• Memory-system architecture

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Computer Memory Overview(1)

• Method of accessing memory
• Sequential access - Tape
• Direct access - Disk
• Random access - RAM
• Associative - Cache
• Which question is important for memory design?
• How much?
• How fast?
• How expensive?
• Three key characteristics
• Faster access time, greater cost per bit
• Greater capacity, smaller cost per bit
• Greater capacity, slower access time

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Computer Memory Overview (2)

• The answer for memory design is Memory Hierarchy
• It results in the followings.
• Decreasing cost per bit
• Increasing capacity
• Increasing access time
• Decreasing frequency of access of the memory by
  the processor

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Memory Implementations

• Read Only Memory (ROM, also RAM)
• Random Access Memory (RAM)
• Static RAM
• Dynamic RAM
• Volatile - requires constant power
• SRAM, DRAM
• Non-volatile not require constant power
• All ROMs

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Types of ROM

• ROM - read only memory (also a form of
  random-access memory). Usually factory
  programmed and unalterable
• PROM - programmable ROM - fuses or burns
  information into the chip, writable once
• EPROM - erasable PROMs - using ultraviolet light,
  the entire PROM can be erased at once
• EEPROM - electrically Erasable PROM - erasable
  maybe 1000 times before they are no good

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Memory Type
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Cache Memory

• One of memory hierarchies
• Cache is high-speed buffer for holding recently
  accessed data and neighboring data in main memory
• Idea behind a cache is to speed up processing
  time by eliminating slow-down for main memory
  access using fast memory
• Principle of locality of reference?

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Principle of locality of reference

• Why does this work?
• Programs tend to execute instructions in sequence
  and hence nearby memory locations
• Programs often have loops in which a group of
  instructions is executed repeatedly
• Most compilers store arrays in blocks of adjacent
  memory locations
• Compilers often place unrelated data items in a
  data segment, thus data is often in consecutive
  memory locations

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Components of cache
Start
CPU wants to access memory

• Two reasons why caches work well
• Operate in parallel with CPU
• Principle of locality of reference
• Cache hit gt 90 is common

CPU sends Physical address to cache
Compare PA To all address tags
Send data From cache to CPU (cache hit)
YES
Load data from memory (cache miss )
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Cache performance

• Time per instruction (TPI)
• TPI TPIbase timememory access

Execution time
T1 cache access time T2 main memory access
time T T1 hit rate (T1T2) miss rate
Main Memory
T1
T2
CPU
HD
T3
Cache
T ? In case of this picture
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Cache Writes

• When do you write data from cache to main memory?
  
• Write through
• copy the new datum both to cache and memory
• Write back
• hold datum until a later time and then write it
  back into memory

Dirty cell
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Cache structure and organization

• There are 2 components
• tag subsystem
• memory subsystem
• A refill line contains to n words (power of 2)

Tag
Refill line
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Types of caches

• Associative
• Direct
• Set-associative

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Associative Cache

• Another name fully associative cache
• To find memory location X in cache, perform
  associative search of cache all tags for X
• Disadvantages - Cache tags require log2N bits
  each and associative memory is more expensive
• N is equal to number of refill lines in main
  memory
• See figure 4.12 page 200

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Direct-mapped Cache

• Cache is divided into N refill lines, each
  storing exactly 1 column of memory
• Cache tag is used to store the column number
• Refill line X, Column I is stored in Cache row X
  with I being stored as the tag
• Disadvantage - can only store 1 column of each
  refill line
• Advantage - do not need associative memory or
  lengthy tags (tag size log2K)

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Set-Associative Cache

• Combines both methods (associative and direct)
• Memory is still partitioned into N refill lines
  and K columns
• Cache contains M columns
• Now, each row in cache can store up to M columns
  instead of 1.
• Tags still store column numbers, but are searched
  associatively since there are M of them
• See figure 4.14 page 201

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Cache-address processing

• Fully associative
• Direct-mapped
• Set associative

Tag
byte
Tag
Line
byte
Tag
Set
byte
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Fully associative
Main memory
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Direct-mapped
Main memory
1 refill line
Example Access byte at 29 th
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Set-associative
Main memory
1 refill line
Example Access byte at 29 th and 13 rd
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Question

• Main memory ???? 64 bytes ?? Cache ???? 16 bytes
  ??? 2-way set associative ??? Line size ??????? 2
  Bytes ????????? address format
• Main memory ???? 1 MB ?? Cache ???? 256 KB ???
  8-way set associative ??? Line size ??????? 32
  Bytes ????????? address format
• Main memory ???? 264 ???? Address format, ???????
  Cache ??? ??????? Tag ??? 4-way set associative
  cache ????? Line size ??? 64 bytes ??? Cache ??
  220 Lines (used to be midterm question)

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Virtual Memory

• Cache provides fast access
• Virtual memory provides capacity

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6.5 Virtual Memory

• Information concerning the location of each page,
  whether on disk or in memory, is maintained in a
  data structure called a page table (shown below).
• There is one page table for each active process.

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6.5 Virtual Memory

• If the valid bit is zero in the page table entry
  for the logical address, this means that the page
  is not in memory and must be fetched from disk.
• This is a page fault.
• If necessary, a page is evicted from memory and
  is replaced by the page retrieved from disk, and
  the valid bit is set to 1.
• If the valid bit is 1, the virtual page number is
  replaced by the physical frame number.
• The data is then accessed by adding the offset to
  the physical frame number.