Wires

1
Wires
2
Introduction

• Chips are mostly made of wires called
  interconnect
• Wires are as important as transistors. They
  impact
• Speed
• Power
• Noise
• In modern technologies (e.g., 0.13 mm)
• Wires are much narrower driving up wire
  resistance
• Wires are much closer resulting in larger
  capacitive coupling and noise (crosstalk)
• In many paths, the wire RC delay exceeds gate
  delay
• Multiple metal layers (e.g., 8) allow higher
  level of integration

3
Wire Geometry

• Pitch w s
• Aspect ratio AR t/w (thickness to width)
• Old processes had AR ltlt 1
• Modern processes have AR ? 2
• Pack in many skinny wires

4
Wire Resistance

• Resistance of a uniform slab of conducting
  material
• r resistivity (Wm)

5
Wire Resistance

• r resistivity (Wm)
• R? sheet resistance (W/?)
• Count number of squares
• R R? ( of squares)

6
Choice of Metals

• Until 180 nm generation, most wires were aluminum
• Modern processes often use copper
• Reduces resistance
• Improves electromigration (current handling
  capability

7
Sheet Resistance

• Typical sheet resistances in 180 nm process

8
Contacts Resistance

• Contacts and vias also have 2-20 W
• Use many contacts for lower R
• Many small contacts for current crowding around
  periphery (non uniform distribution of current
  density or higher current density on the
  periphery)

9
Wire Capacitance

• Wire has capacitance
• To neighbors
• To layers above and below
• Ctotal Ctop Cbot 2Cadj

10
Capacitance Trends

• Parallel plate equation C eA/h (A w l)
• Increasing area (W, l) increases capacitance
• Increasing distance (s, h) decreases capacitance
• Dielectric constant
• e ke0
• e0 8.85 x 10-14 F/cm
• k 3.9 for SiO2
• Processes are starting to use low-k dielectrics
• k ? 3 (or less) to reduce the wiring capacitance

11
Diffusion Polysilicon

• Diffusion capacitance is very high (about 2
  fF/mm)
• Comparable to gate capacitance
• Diffusion also has high resistance
• Avoid using diffusion runners for wires!
• Polysilicon has lower C but high R
• Use for transistor gates
• Occasionally for very short wires between gates

12
Lumped Element Models

• Wires are a distributed system
• Approximate with lumped element models
• 3-segment p-model is accurate to 3 in simulation
• L-model needs 100 segments for same accuracy!
• Use single segment p-model for Elmore delay

13
Example

• Metal2 wire in 180 nm process
• 5 mm long - R? 0.05 W/?
• 0.32 mm wide - Cpermicron 0.2 fF/mm
• Construct a 3-segment p-model
• R (0.05) (5000/0.32) 781 W
• C (0.2) (5000) 1 pF

14
Wire RC Delay

• Estimate the delay of a 10x inverter driving a 2x
  inverter at the end of the 5mm wire from the
  previous example. The gate capacitance is C
  2fF/mm and the effective resistance is R 2.5
  kWmm for NMOS transistors (neglect diffusion
  caps).
• C 2x inverter 6 C 6 2 fF/mm 0.36 mm 4
  fF
• Reff (R 2.5 kWmm) / (10 0.36 mm ) 690 W
• tpd (690 W 500 fF) (690 W 781 W) 504 fF
  1.1 ns

15
Crosstalk

• A wire has capacitance to its neighbor.
• When the neighbor switches from 1-gt 0 or 0-gt1,
  the wire tends to switch too.
• Called capacitive coupling or crosstalk.
• Depends on the wire separation
• Crosstalk effects
• Increased delay on switching wires
• Noise on non-switching wires

16
Crosstalk Delay

• Assume layers above and below on average are
  quiet
• Second terminal of capacitor can be ignored
• Model as Cgnd Ctop Cbot
• Effective Cadj depends on behavior of neighbors
• Miller Coupling Factor (MCF)

17
Crosstalk Noise

• Crosstalk causes noise on non-switching wires
• The crosstalk noise depends on the aggressor and
  victim drive capability.

18
Noise Implications

• So what if we have noise?
• If the noise is less than the noise margin,
  functionality will be o.k. if the delay impact is
  minimal
• Static CMOS logic will eventually settle to
  correct output even if disturbed by large noise
  spikes
• But glitches cause extra delay (which can impact
  functionality)
• Also cause extra power from false transitions
• Memories and other sensitive circuits also can
  produce the wrong answer
• Use wide spacing, wider wire widths, and
  shielding to reduce delay and noise due to
  crosstalk.

19
Repeaters

• R and C are proportional to l (length)
• RC delay is proportional to l2
• Unacceptably great for long wires
• Break long wires into N shorter segments
• Drive each one with an inverter or buffer

20
Repeater Design

• How many repeaters should we use?
• How large should each one be?
• New wire has N segments with RC delay
  proportional to N (l/N)2 l2/N. If N is
  proportional to l, then the overall delay
  increases only linearly with l.
• Equivalent Circuit of one segment
• Wire length l/N
• Wire Capaitance Cwl/N, Resistance Rwl/N
• Inverter width W (nMOS W, pMOS 2W)
• Gate Capacitance CW (C3C), Resistance R/W

21
Repeater Results

• Write equation for Elmore Delay
• Differentiate with respect to W and N
• Set equal to 0, solve

Best length of wire between repeaters
Delay per unit length 60-80 ps/mm in 180 nm
process
NMOS transistor width
22
Design Variation

• Must consider variation in
• Supply voltage
• Operating temperature
• Process
• Impact to gate delay or circuit speed.

23
Supply Variation

• Supply voltage (VDD) varies due to
• Voltage regulator tolerance
• IR drop along supply rails
• L di/dt (transient) noise
• Means need to simulate to /- 10 of VDD
• Gate delay increases as VDD is reduced.

24
Temperature Variation

• Temperature varies due to
• Ambient temperature changes
• Temperature rise caused by power dissipation in
  the package (junction temperature of a transistor
  ambient temperature temperature rise in the
  package).
• Gate delay increases as temperature is increased
  due to reduction in drain current.
• Need to simulate for operating temperature range
  (ambient from 0-70o C commercial, -40-85o C
  industrial, -55-125o C military).
• Can reduce junction temperature using package
  heat sinks, cooling, etc.

25
Process Variation

• Process varies due to
• Variations in dimensions, doping, thickness,
  resulting in transistor variation in channel
  length, oxide thickness, and threshold voltage.
• Variations occur from die to die, wafer to wafer,
  and lot to lot
• OCV (on chip variation meaning variation across
  one die) has become increasingly important in
  state-of-the-art sub-micron technologies
• Interconnect variation in line width and spacing.
• Need to simulate for fast and slow processes

26
Design Corners

• Design Corners (impacts yield)
• Slow
• Low supply voltage
• High temperature
• Slow process
• Nominal
• Typical voltage, temperature, process
• Fast
• High supply voltage
• Low temperature
• Fast process

27
SPICE Simulation
28
Simulators

• Architecture simulators
• High-level programs for verifying architecture
• e.g., C programs, Matlab
• Logic Simulators
• For verifying functional behavior at the RTL
  (i.e., VHDL or Verilog) level
• e.g., Modelsim (from Mentor Graphics), NCSim
  (from Cadence)
• Circuit Simulators
• For simulating at the transistor level
• e.g., SPICE
• Process Simulators
• For simulating process technologies (e.g., effect
  of doping on threshold)

29
Introduction to SPICE

• Simulation Program with Integrated Circuit
  Emphasis
• Developed in 1970s at Berkeley
• Many commercial versions are available
• HSPICE is a robust industry standard

30
Example RC Circuit
rc.sp Cards beginning with are comments
David_Harris_at_hmc.edu 2/2/03 Find the response
of RC circuit to rising input   -----------------
------------------------------- Parameters and
models ------------------------------------------
------ .option post Tells SPICE to write
results to a file for use with a
viewer   ----------------------------------------
-------- Simulation netlist -------------------
----------------------------- Vin in gnd pwl 0ps
0 100ps 0 150ps 1.8 800ps 1.8 R1 in out 2k C1 out
gnd 100f   --------------------------------------
---------- Stimulus ---------------------------
--------------------- .tran 20ps 800ps transient
analysis with a 20ps step size for 800 ps .plot
v(in) v(out) .end
31
Result (Graphical)
32
Sources

• DC Source
• Vdd vdd gnd 2.5
• Piecewise Linear Source
• Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8
• Pulsed Source
• Vck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps
  800ps

33
DC Analysis
mosiv.sp   ------------------------------------
------------ Parameters and models ------------
------------------------------------ .include
'../models/tsmc180/models.sp' Reads another
SPICE file from disk .temp 70 sets temperature
to 70o C .option post   -------------------------
----------------------- Simulation
netlist -----------------------------------------
------- nmos Vgs g gnd 0 Vds d gnd 0 M1 d g gnd g
nd NMOS W0.36u L0.18u   -----------------------
------------------------- Stimulus ------------
------------------------------------ .dc Vds 0
1.8 0.05 SWEEP Vgs 0 1.8 0.3 dc analysis .end
34
I-V Characteristics

• nMOS I-V

35
MOSFET Elements

• M element for MOSFET
• Mname drain gate source body type
• Wltwidthgt Lltlengthgt
• ASltarea sourcegt AD ltarea draingt
• PSltperimeter sourcegt PDltperimeter draingt

36
Transient Analysis
inv.sp   Parameters and models --------------
---------------------------------- .param
SUPPLY1.8 defines a parameter called
SUPPLY .option scale90n Specifies l 90
nm .include '../models/tsmc180/models.sp Reads
a SPICE file from disk .temp 70 sets
temperature to 70o C .option post   Simulation
netlist -----------------------------------------
------- Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0
'SUPPLY' 50ps 0ps 0ps 100ps 200ps M1 y a gnd gnd N
MOS W4 L2 AS20 PS18 AD20 PD18
indicates continuation across multiple
lines M2 y a vdd vdd PMOS W8 L2 AS40 PS26
AD40 PD26   Stimulus ------------------------
------------------------ .tran 1ps 200ps .end
37
Transient Results

• Unloaded inverter
• Overshoot
• Very fast
• edges

38
Subcircuits

• Declare common elements as subcircuits
• Ex Fanout-of-4 Inverter Delay

.subckt inv a y N4 P8 M1 y a gnd gnd NMOS W'N'
L2 AS'N5' PS'2N10' AD'N5'
PD'2N10' M2 y a vdd vdd PMOS W'P' L2
AS'P5' PS'2P10' AD'P5' PD'2P10' .ends
SPICE calculates functions within ''
39
FO4 Inverter Delay
fo4.sp   Parameters and models --------------
--------------------------------------------------
------ .param SUPPLY1.8 defines a
parameter called SUPPLY .param H4
Specifies fanout .option scale90n
Specifies l 90 nm .include '../models/tsmc180/
models.sp Reads another SPICE file from
disk .temp 70 sets temperature to 70o
C .option post   Subcircuits ----------
--------------------------------------------------
---------- .global vdd gnd global nodes that
can be referred within the subcircuit .include
'../lib/inv.sp Reads the INV SPICE file (or
can include here)   Simulation
netlist -----------------------------------------
----------------------------- Vdd vdd gnd 'SUPPLY'
Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps
1000ps X1 a b inv Uses default P
N X2 b c inv M'H' Indicates 4 X2s in
parallel
.end
40
FO4 Inverter Delay Cont.
X3 c d inv M'H2' device under
test X4 d e inv M'H3' load x5 e f inv M'H4
' load on load   Stimulus -------------------
--------------------------------------------------
- .tran 1ps 1000ps .measure tpdr measures
rising prop delay TRIG v(c) VAL'SUPPLY/2'
FALL1 TARG v(d) VAL'SUPPLY/2' RISE1
Trigger points for measurement .measure
tpdf measures falling prop delay TRIG
v(c) VAL'SUPPLY/2' RISE1 TARG v(d)
VAL'SUPPLY/2' FALL1 .measure tpd
param'(tpdrtpdf)/2' average prop
delay .measure trise rise time TRIG
v(d) VAL'0.2SUPPLY' RISE1 TARG
v(d) VAL'0.8SUPPLY' RISE1 .measure tfall
fall time TRIG v(d) VAL'0.8SUPPLY'
FALL1 TARG v(d) VAL'0.2SUPPLY' FALL1 .end
41
FO4 Results
42
Optimization

• HSPICE can automatically adjust parameters
• Seek value that optimizes some measurement
• Example Best P/N ratio
• Weve assumed 21 gives equal rise/fall delays
• But we see rise is actually slower than fall
• What P/N ratio gives equal delays?
• Strategies
• (1) run a bunch of sims with different P size
• (2) let HSPICE optimizer do it for us

43
P/N Optimization
fo4opt.sp   Parameters and models -----------
--------------------------------------------------
--------- .param SUPPLY1.8 .option
scale90n .include '../models/tsmc180/models.sp' .
temp 70 .option post   Subcircuits ------------
--------------------------------------------------
-------- .global vdd gnd .include
'../lib/inv.sp' Simulation netlist -----------
--------------------------------------------------
--------- Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0
'SUPPLY' 0ps 100ps 100ps 500ps 1000ps X1 a b inv P
'P1' Override PMOS width with P
P1 X2 b c inv P'P1' M4 X3 c d inv P'P1' M16
device under test
44
P/N Optimization
X4 d e inv P'P1' M64 load X5 e f inv P'P1' M
256 load on load   Optimization
setup -------------------------------------------
--------------------------- .param
P1optrange(8,4,16) search from 4 to 16, guess
8 .model optmod opt itropt30 maximum of 30
iterations .measure bestratio param'P1/4'
compute best P/N ratio   Stimulus -------------
--------------------------------------------------
------- .tran 1ps 1000ps SWEEP OPTIMIZEoptrange
RESULTSdiff MODELoptmod .measure tpdr
rising propagation delay TRIG
v(c) VAL'SUPPLY/2' FALL1 TARG v(d)
VAL'SUPPLY/2' RISE1 .measure tpdf falling
propagation delay TRIG v(c)
VAL'SUPPLY/2' RISE1 TARG v(d)
VAL'SUPPLY/2' FALL1 .measure tpd
param'(tpdrtpdf)/2' goal0 average prop
delay .measure diff param'tpdr-tpdf' goal 0
diff between delays .end
45
P/N Results

• P/N ratio for equal delay is 3.61
• tpd tpdr tpdf 84 ps (slower than 21 ratio)
• Big pMOS transistors waste power too
• Seldom design for exactly equal delays
• What ratio gives lowest average delay?
• .tran 1ps 1000ps SWEEP OPTIMIZEoptrange
  RESULTStpd MODELoptmod
• P/N ratio of 1.41
• tpdr 87 ps, tpdf 59 ps, tpd 73 ps

46
Power Measurement

• HSPICE can measure power
• Instantaneous P(t)
• Or average P over some interval
• .print P(vdd) measure inst. Power delivered
  by Vdd
• .measure pwr AVG P(vdd) FROM0ns TO10ns
• Power in single gate
• Connect to separate VDD supply

47
Logical Effort

• Logical effort can be measured from simulation
• As with FO4 inverter, shape input, load output

48
Logical Effort Plots

• Plot tpd vs. h
• Normalize by t
• y-intercept is parasitic delay
• Slope is logical effort
• Delay fits straight line
• very well in any process
• as long as input slope is
• consistent
• d 1.93 1.1h from plot
• d 2 1.3h from RC delay analysis

t 15 ps
49
SPICE Device Models

• Level 1
• Closely related the the Shockley model discussed
• Enhanced with channel length modulation and drain
  induced barrier lowering
• Enhanced with the body effect
• Level 2 and 3
• Enhanced with velocity saturation, mobility
  degradation, and subthreshold conduction.
• Level 3 allows faster simulations and better
  convergence
• BSIM models
• Are derived from device physics, are very
  complex, and use large number of parameters (
  100) to fit the behavior of modern transistors
• Are needed for accurate simulation of sub-micron
  technologies

50
Design Corner SPICE Deck
corner.sp   Spec response of unloaded
inverter across process corners -----------------
------------------------------- .option scale90n
Specifies l 90 nm .param SUPPLY1.8 Must
be set before calling .lib .lib
'../models/tsmc180/opconditions.lib TT invoke
the library card read in TT .option post  
Simulation netlist ------------------------------
------------------ Vdd vdd gnd 'SUPPLY' Vin a gnd
PULSE 0 'SUPPLY' 50ps 0ps 0ps 100ps
200ps M1 y a gnd gnd NMOS W4 L2 AS20 PS18
AD20 PD18 M2 y a vdd vdd PMOS W8 L2 AS40
PS26 AD40 PD26   Stimulus ------------------
------------------------------ .tran 1ps
200ps .alter repeat simulations for a
different corner
51
Design Corner SPICE Deck cont.
.lib '../models/tsmc180/opconditions.lib FF
invoke the library card read in FF .alter .lib
'../models/tsmc180/opconditions.lib SS invoke
the library card read in FF   .end
52
OPCONDITIONS Library

• Opconditions .lib for TSMC 180 nm process
• TT typical NMOS, PMOS, Voltage, Temperature
• .lib TT
• .temp 70
• .param SUPPLY 'SUPPLY
• .include modelsTT.sp
• .end TT
• SS Slow NMOS, PMOS, Low Voltage, High
  Temperature
• .lib SS
• .temp 125
• .param SUPPLY 0.9 SUPPLY
• .include modelsSS.sp
• .end SS
• FF Fast NMOS, PMOS, High Voltage, Low
  Temperature
• .lib FF
• .temp 0