Implementation of 5

1
Implementation of 5 Stage Pipeline with VAB

• -Pradnyesh Gudadhe
• -Saleel Kudchadkar

2
Goals Achieved

• Integrated VAB in 5-stage pipeline
• Implemented VAB that supports Location Bit.
  (Additional task. Not planed initially) An effort
  to save 1 cycle penalty of VAB miss.
• Able to show reduced number of accesses to
  Register File because of VAB.

3
Goals not achieved

• Unable to reduce number of ports required by VAB.
  VAB is really port hungry.
• (Thats the Reason for VAB being not accepted
  by commercial processor manufacturers.)
• Unable to verify power statistics.
• (Was not on project plan.)

4
Assumptions

• The 5-stage pipeline supports various simple
  instructions like, ADD, SUB, BEQ, ANDi, ORi, LW,
  SW, NOR, ADDiu.
• The claims of the research paper on VAB are not
  assumed to be true. We intend to validate and
  verify them in order to get explanations for the
  questions raised during class presentation.
• The register file contains 32 physical registers
  hence experimental Value Aging Buffer would be
  having 8 entries in it.

5
Project Plan

• Problem Description Implementing register file
  power reduction technique.
• Plan
• 1) Studying register file power consumption
  issues (1 Week)
• 2) Studying Register File power reduction using
  value lifetime characteristics
• 3) Studying Register File power reduction by
  bypass aware instruction scheduling
  (2 Weeks)
• 4) Planning and estimating feasibility of
  implementing both methods
• 
  (1
  Week)
• 5) Start implementation using Verilog in 5-stage
  pipeline (2 Weeks)
• 6) Collect data regarding register files
  accesses.
• 7) Data Analysis
• 8) Compile report (1
  Week)

6
What have we learnt?

• Identifying exact, strategic placement of VAB in
  datapath
• Analysis of register file accesses data
• Impact of VAB on performance
• Experience of actually implementing theory
  proposed by the paper.
• Validating proposed theory
• Verifying functionalities of VAB

7
Results

• Without VAB
• Register File IN 47, OUT 64
• Total 111
• With VAB
• Register File IN 50, OUT 64
• Location Map IN 26, OUT 3
• VAB IN 113, OUT 76
• Total 332
• No. of ports increased by 3 times !!??

8
Results

• No. register accesses reduced by approximately
  50-70
• On die memory requirement increased by
• (32 42 x n) Bits
• (n No. of entries in VAB )

9
Future Work Opportunities

• Reducing number of ports required because of VAB
  is a challenging research area.
• Success in this topic could be a major
  break-through in Register File Ports Reduction
  and Power Density Relaxation.

10
THANK YOU!?Questions?
11
Backup slides
CLK
CLR
LOC1
Location MAP
RREG1
LOC2
LOC3
RREG2
WREG
CLK
CLR
LOC3
LOC2
LOC1
RegWr
REGISTER FILE
RREG1 04
Evict1 04
Reg1 Out
RREG2 04
Evict2 04
Reg2 Out
WREG 04
Evict3 04
WDATA 031
LOC3
LOC2
LOC1
CLK
CLR
RegWr
VALUE AGING BUFFER
RREG1
Reg1 Out VAB
MUX
RREG2
Reg2 Out VAB
MUX
WREG
WDATA