Memory Modeling

1
Memory Modeling
2
Memory Delcaration

• Verilog models memories as an array of registers.
• Examples
• reg 70 mema 0255 //256 x 8-bit memory
  array
• reg 70 PLA hFFFEhFFFF //2 x 8-bit memory
  array

parameter wordsize16, memsize256 reg
wordsize-10 mem_word,
mem_arraymemsize-10
3
Memory Addressing

• A memory element is addressed by giving the
  location of memory array

reg 81 mem_word, mem_array0255 //assign
a value to memory element mem_array0
8b0010_1100 //display the content of the 8th
memory element displayb(mem_array7) //displa
y the MSB of the 8th memory element mem_word
mem_array7 displayb(mem_word8)
4
Modeling a ROM
5
Loading a Memory Array

• Use readmem system task to load values from a
  text file into memory array
• readmemltbasegt(ltfile_namegt,ltmem_namegt,ltstartgt?,lt
  finishgt? )

reg 70 mem 1256 initial
readmemh(mem.data,mem) initial
readmemb(mem.data,mem,16) initial
readmemh(mem.data,mem,18,256)
6
File Format for readmemb/readmemh
reg 70 mem 01023 initial
readmemb(mem.data,mem)
0000_0000 0100_1000 0101_1010 //address 3 to 255
are not defined _at_100 1010_1111 //address 257 to
1022 are not defined _at_3FF 1010_0010
7
Modeling a RAM

• Modeling an Asynchronous RAM

8
Modeling Bi-Directional Ports

• The bi-directional ports need to be declared
  using the keyword inout
• Inout ports must follow the rules
• The inout ports must be driven by a net not by a
  register
• The inout ports must drive a net but not a
  register
• Logic gates need to be built around the inout
  ports to ensure proper operations

9
Modeling Bi-Directional Ports
module RAM2x2(DATA,ADDR,read,write) inout 10
DATA inout 10 ADDR input read,write reg
10 intBus, ram_core30 wire 10
data_wr bufif1(DATA0,intBus0,read) bufif1(D
ATA1,intBus1,read) bufif1(data_wr0,DATA0,
write) bufif1(data_wr1,DATA1,write) always
_at_(posedge read) assign intBus
ram_coreADDR always _at_(posedge write) assign
ram_coreADDR data_wr endmodule
module RAM2x2(DATA,ADDR,read,write) inout 10
DATA inout 10 ADDR input read,write assign
DATA10 (read1) ? ram_coreADDR
2bz always _at_(posedge write) assign
ram_coreADDR DATA endmodule