Design Strategies

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Design Strategies
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Sources of Information

• This section draws on Dr. McInnes notes and on
  the textbook, but also on
• http//lsiwww.epfl.ch/LSI2001/teaching/webcourse/c
  h01/ch01.html

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Design Hierarchies

• There are three domains to the design problem
• Behavioural from instructions to applications,
  i.e. software
• Structural from transistors via components
  e.g. adders to processors
• Physical from transistors via cells to chips,
  boards etc.
• A good design system provides consistent
  descriptions in all three domains. How?
• Simplify the problem by means of
• Constraints raise the possibility of automating
  procedures
• Abstractions collapse detail to allow a
  simpler concept with which to deal
• A structured approach offers best prospects for
  large VLSI problems.

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Hierarchical Decomposition

• In other words divide and conquer
• Progressively decompose modules to comprehensible
  sub-modules
• Cease decomposition where modules are defined in
  terms of simulation models and physical layouts
• And at a comprehensible level of detail
• This approach also allows the schedule to become
  proportional in duration to the size of the
  design team since (sub-)modules can be allocated
  to individual personnel.

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Useful Constraints - 1

• Regularity
• divide the hierarchy into similar 'building
  blocks, e.g.
• at circuit level use uniformly sized transistors
• at logic level use identical gate structures
• Locality
• definition of interfaces effectively hides
  internal complexity
• (equivalent to reduction of global variables in
  software)

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Useful Constraints - 2

• Modularity
• Sub-modules have well-defined functions and
  interfaces
• The information given will include e.g. position,
  name, layer type, size, logic function, etc.
• 3 basic constructs
• (i) cell abutment
• cells in physical domain connected by placing
  them adjacent
• (ii) iteration
• one and two-dimensional arrays of identical
  cells.
• (iii) conditional selection
• Typified by a programmable logic array (PLA) the
  function of which is determined by location of
  transistors

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Chip Design Options

• Programmability achieves wider usage
• Achieve via
• programmable logic structures (PLS)
• programmable interconnect (PI)
• reprogrammable gate arrays (RGA)

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Programmable Logic Structures (PLS) - 1

• also loosely referred to as
• PAL (Programmable Array Logic)
• PLD (Programmable Logic Device)
• AND and OR gates in sum-of-products arrays
• Connections made/broken by
• i) fusible links (one-time only)
• ii) UV erasable PROM
• iii) electrically erasable PROM
• Any Boolean function can be programmed into a PLS

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Programmable Logic Structures (PLS) - 2

• Various conventions apply
• PROM fixed AND, programmable OR
• all product terms available
• PAL programmable AND, fixed OR
• compromise between PROM and FPLA
• FPLA programmable AND and OR
• more flexible than PROM only those product
  terms required need be selected
• Slower than PROM

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Programmable Logic Structures (PLS) - 3

• e.g.

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Programmable Logic Structures (PLS) - 4

• UV - Erasable
• uses a floating gate structure
• 15 V to control gate, drain held at 10 V
• Hence the floating gate becomes permanently
  negatively charged and VT increases to 7 V
  (i.e. permanently OFF).
• Charge will leak away (permanently means at
  least 10 years at 125oC)
• Basis is the FAMOSFET
• (Floating-gate Avalanche MOSFET)
• Reverse programming by 30 minutes exposure to
  UV light (? 253.7nm) at a distance of approx
  2.5cm.
• After programming, cover the quartz window to
  exclude UV light.

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Programmable Logic Structures (PLS) - 5

• Electrically Erasable
• basis is FAMOSFET
• programmed as for UV - erasable
• Reverse programming is achieved by allowing
  trapped electrons to tunnel from the floating
  gate and hence turning the cell ON

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Programmable Interconnect

• Here the routing is programmed instead of the
  switching element
• uses antifuses or PLICEs
• (Programmable Low-Impedance Circuit Element)
• Logic elements arranged in rows
• permanent interconnect vertically
• programmable interconnect horizontally

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Reprogrammable Gate Arrays - 1

• a) Adhoc Structures
• Xilinx PGA
• array of configurable logic blocks (CLBs)
  embedded in horizontal and vertical channels
• interconnect achieved via n-channel pass
  transistors
• map logic design to CLBs
• CLB contains (e.g.)
• 2 registers
• multiplexer
• combinatorial function unit (to generate
  functions of 4 or 5 variables)

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Example Xilinx FPGAs
General Architecture
XC2000 CLB
Detail of switch matrices and interconnection
routing
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Reprogrammable Gate Arrays - 2

• b) Regular Structures
• e.g. Algotronix Configurable Array Logic
• 1024 identical logic cells in 32 x 32 matrix
• programmable I/O pins allow larger arrays
• each cell connects N, S, E, W plus 2 global
  interconnects plus lines to program RAM within
  the cell
• logic cell functions include
• -x1. x2 -x1 . -x2
• x1 x2 x1 -x2
• -x1 x2 XNOR (x1, x2)
• -x1 -x2 XOR (x1, x2)

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Gate Arrays

• A design on FPGAs is achieved by user
  programming for a Gate Array it is done with
  metal mask design and processing.
• Gate Array implementation requires a 2-step
  manufacturing process
• The first is based on generic (standard) masks
• This results in an array of uncommitted
  transistors on each GA chip
• such chips can be stored for later customisation
• The second defines the metal interconnects
  between the transistors in the array
• Since patterning of the metallic interconnects is
  done at the end of chip fabrication the turn
  around time can be short days or weeks

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Sea of Gates - 1

• The chip core f or this approachcontains a
  continuous array of n and p transistors
• Customisation is achieved via design-specific
  metallisation
• The core is surrounded by an array of I/O cells
• Routing channels route over top of unused
  transistors
• In earlier technology gate-array structures,
  routing was confined to dedicated routing
  channels.
• For customisation one can use
• single-layer metal
• single-layer metal contacts
• double-layer metal, contact, vias
• triple-layer metal, contacts, vias

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Sea of Gates - 2
Sea of Gates Chip Layout
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Example 3-input NAND
Schematic metallisation for a SOG 3-input NAND
gate F A.B.C
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Sea of Gates - 3

• Gate counts can be high
• Given a column pitch 10 microns row pitch 100
  microns
• an 8mm by 8 mm core has 64,000 transistors
• i.e approx 16,000 2-input NANDs
• with 40 usability (due to routing over unused
  transistors) this comes to approx 6400 gates

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Standard Cell Design

• standardise at logic level by creation of library
  cells
• e.g. NAND, NOR
• decoders, adders
• RAM/ROM blocks of memory
• multipliers
• capture design using standard cells
• adopt automatic placement and routing (CAD
  software)
• cells should maximise performance and minimise
  parasitic effects
• Note the contrast with Full Custom Design which
  involves optimisation of function and layout of
  every transistor! This is not in general feasible

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Symbolic Layout

• Abstract from the physical layout to reduce
  complexity of entry.
• Several strategies evolved
• e.g. STICKS and COMPACTION
• (i) draw a sketch of the layout with coloured
  lines to represent different layers.
• This represents an approximate topology.
• (ii) a spacing (or compaction) program determines
  correct spacing between wires, transistors and
  contacts.

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Design Methods - 1

• Behavioural Level Synthesis
• system operation captured without specification
  of implementation
• Register Transfer Level (RTL) Synthesis
• capture description with HDL (e.g. VHDL)
• RTL compiler converts a description in an HDL
  into a set of registers and combinational logic

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Design Methods - 2

• Logic Optimisation
• take relevant output from RTL synthesis and
  optimise the required network of gates
• a) technology-independent
• optimize logic
• b) technology-mapping
• relate to specific library
• of standard-cells/FPGA elements etc

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Design Methods - 3

• Structural to Layout Synthesis
• conversion of network to layout
• a) Placement
• to minimise area or cycle time
• b) Routing
• connects modules with wires

• Layout Synthesis
• layout of regular structures can synthesised by
  software
• automatic creation of custom physical layout
• used when a simple algorithm can specify the
  layout

• It is sensible to use a suite of Design Capture
  Tools

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HDL Design

• use a hardware description language (HDL)
• e.g. VHDL, ELLA, Verilog
• HDLs cater for bit vectors, signals and time
  within their syntax
• HDLs provide all elements of modern programming
  languages
• (structure, conditionals, looping, hierarchy,
  parameterisation)

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Schematic Design

• use an interactive schematic editor
• draw, define and connect components
• create, select and delete components
• zoom in, pan across
• select electrical node and interrogate

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Layout Design

• Use a colour graphics editor
• interface to a design rule checking program to
  check DRC errors
• interface to a layout-extraction program to
  examine circuit connectivity issues
• Floorplanning
• to arrange blocks within the chip to minimise
  area or maximise speed
• also show module connectivity information

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Design Verification Tools - 1

• Use Simulation
• To predict and verify circuit performance
• i) at circuit-level e.g. SPICE
• most detailed and accurate
• long simulation times
• solves matrix equations which are functions of
  V,I,R
• tsimulation ? N12 where N is the number of
  devices
• Therefore not realistic for large VLSI chips
• different levels of modeling (analytic, 2nd order
  effects etc)
• errors arise due to
• a) inaccuracies in the model parameters
• b) inappropriate MOS model
• c) inaccuracies due to parasitics

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Design Verification Tools - 2

• ii) Timing simulation e.g. MOTIS
• simplifies the full circuit analysis approach
• use MOS-model equations to calculate device
  currents
• accuracy less than SPICE but 100 times faster
• relative accuracy usually good
• allow 1020 margin in assessing speeds

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Design Verification Tools - 3

• iii) Logic-level simulation
• use NOT, NAND, NOR etc. as primitives
• Some assume unit delay/gate, others use timing
  parameters based on circuit simulation and known
  parasitics
• It is assumed that Tgate Tintrinsic CL x
  TL
• Tgate delay of the gate
• Tintrinsic intrinsic (no load) delay
• CL load capacitance
• TL delay per load
• Can refer to 'normalised gates' - minimum gate
  load of smallest inverter in a standard-cell
  library and characterise other gates in terms of
  these
• Logic Simulators are adequate for
  well-characterised CMOS circuits with regular
  logic
• relatively fast and so suitable for large circuits

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Design Verification Tools - 4

• iv) Switch-level simulation eg. RSIM
• These model transistors as switches
• it is a merging of logic-simulator techniques
  with circuit-simulation techniques
• CMOS gates modeled as pull-up or pull-down
  structures, with resistance calculated
  dynamically
• fairly pessimistic predictions are produced
  generally
• use as first line of defence
• it is probably best to back up such simulations
  with a reduced set using a timing simulator

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Design Verification Tools - 5

• v) Mixed-mode simulation
• These merge the good points of (i)-(iv) above
• each circuit block simulated at appropriate level
• e.g. standard cell at logic-level
• memory at functional level
• This gives an accuracy/simulation time trade-off

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Summary of Simulation Tools

• Logic Simulator
• well-characterised gates and functional blocks
• use at system level
• Timing Simulator
• for design down to transistor level for most
  digital and some analog circuits
• use for 100 100,000 transistors
• Circuit Simulator
• (when calibrated) accurate for most complicated
  analog circuits
• use for 10 1000 transistors for short
  simulation periods

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Timing Verifiers

• delays through all paths in a circuit are
  evaluated
• functions at gate or transistor level
• initial static analysis to determine direction of
  signal flow
• ? RC delay for each node
• transistor level
• feedback about critical paths
• gate level
• quality of design down to gate level
• pitfalls include
• false paths (lack of knowledge of how circuit is
  used)
• sneak paths (not recognised by analyser)
• perform timing simulations as cross-check

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Network Isomorphism

• map electrical network onto a graph
• Devices (MOS transistors, bipolar transistors
  resistors etc.) ? vertices
• connections between devices ? arcs
• IF
• graphs are isomorphic
• i.e. same number of devices
• matching devices in each circuit
• Device Properties
• transistor width and length
• resistance value
• number of connections
• matching nodes in each circuit
• Node properties
• Same number of source and drains attached to them
• Same number of gates

• THEN
• the electrical circuits are identical
• This is used to prove equivalence of two networks
• e.g. layout - HDL netlist equivalence
• Subnetworks may be used as devices
• e.g. standard-cell blocks

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Netlist Comparison

• to verify equivalence/lack of equivalence of
  circuit graphs
• determine
• fan-in
• fan-out
• transistor-type
• for each transistor
• GEMINI package performs netlist comparisons
• IEEE International Conference on CAD 1983

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Layout Extraction

• examine inter-relationships of mask layers to
  infer existence of transistors
• algorithms use geometric shape intersections to
  recognise active devices
• related to design-rule checkers

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Design Rule Verification

• Checks whether the layout conforms to the
  geometric design rules
• Hierarchical checkers are necessary for large
  circuits

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Back-Annotation

• after layout construction and isomorphism between
  schematic and layout
• correlate extracted capacitances and perform
  simulation/timing analysis to verify performance
• move capacitance on layout node to corresponding
  schematic node whilst accounting for existing
  capacitance on schematic node

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Pattern Generation

• The operation of creating the data used for
  mask-making
• electron-beam-generated masks
• expose resist-coated metal film with focused
  electron beam
• steps include
• layer combination for mask
• Allow for shrink/bloat because of under-etching
  or sideways diffusion
• represent geometry in terms of base figures
• sort shapes in scan-line order (scans as a TV
  picture)
• determine mask polarity (dark or light)
• output data - for ultimate processing

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Data Sheets

• describe what an integrated circuit does
• outline specifications
• i) SUMMARY
• name, functionality, features high-level block
  diagram
• ii) PIN OUT
• pin name, type (input, output, tristate etc)
  description, package pin number
• iii) DESCRIPTION OF OPERATION
• programming options, data formats, control
  options
• iv) DC SPECIFICATIONS
• Supply voltage, pin voltages, junction
  temperature
• VIL and VIH for each input
• VOL and VOH for each output
• quiescent and leakage currents
• input loading
• output drive capabilities

• Communicates power dissipation and required
  voltages
• v) AC SPECIFICATIONS
• Set-up and hold times on all inputs (slowest and
  fastest)
• clock to output delay times (slowest and fastest)
• other critical timing (e.g. minimum pulse width)
• vi) PACKAGE DIAGRAM
• diagram of package with pin names attached

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Design Economics

• may guide the choice of an implementation
  strategy
• may cover
• i) non-recurring engineering costs
• e.g. cost of ATPG equipment
• ii) recurring costs
• iii) fixed costs
• plus
• schedule and manpower implications