Field Programmable Pixel Arrays

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Field Programmable Pixel Arrays

• Jason F. Cantin, Fred R. Beyette Jr.
• University of Cincinnati
• 6/2/2000

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Benefits of using light

• Optics allow for massive parallelism and data
  transfer rates not practical with conventional
  electronics
• Light can be used to carry large amounts of
  information over long distances with little
  attenuation and noise (e.g. fiber-optic cables)
• Light has some interesting properties that can be
  exploited for computing purposes

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CMOS Optoelectronics

• We can combine optical devices with CMOS circuits
  to exploit the properties of both
• The computing power of CMOS can be used to
  enhance the performance of optics (programmable
  optics, electronic control,etc).
• The parallelism and data transfer capabilities of
  light can be used to improve bandwidth and
  communication latency in electronic systems.
• Optics and CMOS can be combined on a single chip.

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Field Programmable Gate Arrays

• Arrays of uncommitted logic elements that can be
  interconnected to make complete circuits.
• A string of bits defines the function of the
  individual logic elements, and their
  interconnections.
• The user can specify a design in a high-level
  language such as VHDL, and use CAD tools to
  generate the strings that program the FPGA.
• Both the user design, and the device are easily
  re-used.

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Field Programmable Pixel Arrays

• Combine the flexibility and reconfigurability of
  FPGAs with the ability to use other types of
  energy
• Add sensors and emitters for improved bandwidth
  over conventional FPGA-based designs
• Optics can be used for fast, parallel
  reconfiguration
• Rapid, low-cost development of real-time
  prototypes for multi-technology systems

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Symmetric Array Example
I/O Blocks
Routing channel
CMOS Logic Block
Reconfigurable Sensor Block
--Structure can be the same as that of a
conventional FPGA, with sensors and emitters
interspersed in the array
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Advantages for Optical Computing

• High-level languages such as VHDL can be used to
  specify optical computing/smart pixel systems.
• May use pre-existing CAD/synthesis tools for
  application development.
• User designs can be technology independent, and
  easily mapped onto larger/improved FPPAs later.
• Much lower cost than custom fabricated designs

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First Implementation Crowbar

• Small (34) array with 8 logic-blocks.
• Four sensor-blocks, with programmable optical
  receivers.
• Photodiodes used as optical detectors
• Optical and electronic reconfiguration.
• Nearest-Neighbor inter-block connections only (no
  global routing structure).

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Crowbar Layout
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Crowbar Logic-Block Organization
INPUTS (NS, NEWS, NEWS)
Configuration in
Clocks, A B
Config. Enable
(Mux controls, --independent)
3-input lookup table
(LUT Entries)
Scan chain in
Test
FF
User Reset
Scan chain out
Configuration Out
OUTPUT (To nearest neighbors)
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Crowbar Logic-Block Characteristics

• 32 Possible logic functions on three inputs
• 3 Inputs can be selected from the 4 nearest
  neighbors, and past outputs
• Each block contains a flop with reset
• Maximum Delay of 19.3 nS
• Minimum Delay of 6.6 nS
• 14 Bits of configuration data required

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Crowbar Logic-Block Layout
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Crowbar Sensor-Block Organization
Configuration in
Config. Clocks, A B
Config. Enable
Config. Optically
RECV
SENSOR (Photodiode)
(3 bits ? 8 possible thresholds)
Scan chain in
Test
N, E, W, S, ClkA, ClkB
FF
User Reset
Scan chain out
OUTPUT
Configuration Out
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Crowbar Sensor-Block Characteristics

• 8 Possible Thresholds for the detector
• Data from neighboring blocks can pass through if
  sensor is not needed
• Contains a flop with reset
• 6 Bits for configuration data required
• Detector and Receiver are slow 500kHz to 1Mhz
  maximum frequency
• 50 to 100 logic gates/cycle

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Receiver Data (simulated)
0.23 Amps/Watt from photodiode, 100-300 nA range
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Crowbar Sensor-Block Layout
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FPPA Project Status

• Project began 2/25/2000
• Prototype design submitted to MOSIS service on
  5/30/2000
• First 5 parts expected in August
• Concept paper in progress

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Future Work

• Compiler support for prototype device (VHDL,
  Verilog, or other industry-standard language)
• A larger device with more sensors, more logic,
  emitters, and embedded RAM on a single chip
• Add hardware to all Partial Reconfiguration and
  Run-time Reconfiguration
• Spatial light modulator for programming and
  transmitting optical data to device

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The master plan A Taxonomy of Reconfigurable
Multi-technology Devices
Optically Reconfigurable
Electrically Reconfigurable (Only)
Dynamically Reconfigurable
Static
Statically Reconfigurable
Dynamic
Partially Reconfigurable
Fully Reconfigurable
Full
Partial
?
Configurable Architecture for Smart Pixel
Research (CASPR)
Crowbar (First FPPA)
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The End.

• You can go home now.