Chapter 05 Tutorial Using HDL Based Design

1
Chapter 05Tutorial Using HDL Based Design

• Verilog Language

2
Objective

• This tutorial will give you exposure to using HDL
  based design
• Using Verilog and Modelsim for simulating the
  functional design
• This tutorial shows you how to create, using
  Verilog, a simple combinational logic circuit
  design

3
Logic Function
F(xy)(yz)
4
Logic Circuit
5
Implementation Methods

• Method 1 Using the automatic module generator
• Method 2 Using the user free input

6
Method 1

• Using the automatic module generator

7
Create a New Project
8
Enter a Name and Location for the Project
9
Select the Device and Design Flow for the Project
10
Create a New Source
11
Select Verilog Module and Enter File Name
12
Define Verilog Source
13
New Source Information
14
Finish
15
Next Step
16
Input Logic Function
17
Add Test Bench Source
18
Add Test Bench Waveform
19
Select Source File
20
New Source Information
21
Initialize Timing
22
Waveform Created by HDL Bencher
23
Save the Waveform
24
View Behavioral Text Fixture
25
Simulate Behavioral Model
26
ModelSim Windows
27
Wave Window
28
Verifying the Logic Function F(x y)(yz)
29
Question and Answer
30
Method 2

• Using the user free input

31
Design a Logic Circuit
32
Create a New Project
33
Enter a Name and Location for the Project
34
Create a New File
35
Free Input Verilog Language in the New File
36
Design Using RTL Level
37
Design Using Gate Level
38
Save the Design
39
File Name complogic1.v

• Module name and File name must the same.

40
Add Source into the Project
41
Select complogic1.v
42
Choose Source Type
43
Add New Source for Test Bench Waveform
44
Select Test Bench Waveform
45
Initialize Timing
46
Waveform Created by HDL Bencher
47
Giving Input Values
48
Save the Waveform
49
Select View Behavioral.. and Run
50
See a HDL Test bench
51
Select Generate Expected.. and Run
52
Verifying the Function of F(x y)(yz)
53
Question Answer