Hardware Description Languages

1
Hardware Description Languages

• Christian Werner
• 06.11.2003

2
Overview

• 1. Introduction
• 2. Hardware Description Languages
• - Modules, Methods, Abstraction Levels
• 3. VHDL
• - History and Standards, Concepts of VHDL
• 4. Verilog
• - History and Standards, Concepts of Verilog
• 5. EDIF
• - History and Standards, Levels, File Structure
• 6. Further languages
• 7. Conclusion

3
Introduction

• Division of system design
• Development process
• idea/requirements ? informal description ? formal
  specification ? defining functions ? RT design ?
  gate design ? layout ? manufacturing

4
Hardware Description Languages (HDL)
"Can anyone understand a system that is only
described by NAND gates? ? Use
modules! DefinitionAn enclosed subsystem with
defined functions is called module. Advantages
Makes the system easier to understand
Division of labour Hierarchical structures
Increases system quality (expandability,
testability, maintenance, reuse)
5
Methods for System Design

• Modelling
• Represents relevant information
• Goal formal specification that is complete,
  definite and consistent
• Modelling for simulation / synthesis
• Simulation
• Compare result ? expected result
• Synthesis
• Model transformation between abstraction levels
  (synthesis input model ? output model)

6
Abstraction Levels

• 1. Behavioural Level
• Functional description of the model
• Model can be simulated
• Model is not synthesizable

7
Abstraction Levels (2)

• 2. Register-Transfer Level (RTL)
• Time (CLOCK, RESET for FF)
• StructuresDifferencing between storing (FF,
  Latch) and nonstoring (combinational logic)
  elements
• ? Formal specification
• ? Simulation and synthesis possible

8
Abstraction Levels (3)

• 3. Gate Level
• ASIC (Application Specific Integrated Circuit)
• Result of RT synthesis Gate Netlist
• Project RT functions on elements of a cell
  library like ASIC
• Netlist contains logic gates and storing elements
• Simulation with respect to gate delay
• 4. Switch Level
• Chip layout
• Complete simulation possible, but in practice not
  done

9
Agenda
1. Introduction 2. Hardware Description
Languages - Modules, Methods, Abstraction
Levels 3. VHDL - History and Standards,
Concepts of VHDL 4. Verilog - History and
Standards, Concepts of Verilog 5. EDIF - Histor
y and Standards, Levels, File Structure 6. Furthe
r languages 7. Conclusion
10
VHDL - History

• VHDL VHSIC HDL Very High Speed Integrated
  Circuit HDL
• Early '70s Initial discussions
• Late '70s Definition of requirements
• Mid - '82 Contract of development with IBM,
  Intermetrics, TI
• Mid - '84 Version 7.2 released by government
• Mid - '86 Proposal for IEEE-Standard
• 1987 DoD adopts the Standard IEEE.1076-1987
• Mid - '88 Increasing support by CAE
  manufacturers
• Late '91 Revision
• 1993 New standard IEEE.1076-1993
• 1999 VHDL-AMS (Analog Mixed Signal) extension
• IEEE 1076.1-1999

11
VHDL Structure

• Entity
• Architecture

entity HALFADDER is port ( A,B in bit
SUM,CARRY out bit )end entity HALFADDER
? defines system interface
architecture NAME of ENTITYNAME is --
declarative part (data types, -- constants,
signals, components)begin -- definition
partend entity HALFADDER
12
VHDL Structure (2)

• Component
• Process
• Concurrent assignments
• Processes
• Sequential assignments
• Sensitivity List

Modul declaration component HALFADDER port (
A,B in bit SUM,CARRY out bit )end
component
Modul instantiation MODULE1 HALFADDERport map
(A,B,W_SUM,W_CARRY1)
Process in VHDL PROCNAME process (LIST)begin
-- sequential assignmentsend process PROCNAME
13
VHDL - Concepts

• VHDL supports
• The module and hierarchy concept
• Abstraction Levels
• Behavioural Level
• Simulation with configuration statement
• RTL
• Combinational and Clocked Processes
• Complete if-clauses in processes ? latch /
  flip flop
• Gate Level
• Code created by synthesis
• No support for layouting a design

14
VHDL - Example

• Behavioural Level

entity full_adder is port ( a in
std_logic b in std_logic ci in
std_logic s out std_logic co out
std_logic )end entity HALFADDER architecture
rtl of full_adder isbegin s lt a xor b xor
ci co lt (a and b) or (a and ci) or (b and
ci)end rtl
15
VHDL - Example (2)

• Gate Level

architecture gate_level of full_adder is
component an02d1 port(a1,a2 in bit z out
bit) end component component xo02d1
port(a1,a2 in bit z out bit) end component
component or03d1 port(a1,a2,a3 in bit z out
bit) end component signal net1, net2, net3,
net4 bit begin U1 xo02d1 port map
(a,b,net1) U2 xo02d1 port map (ci,net2,s) --
sum U3 an02d1 port map (a,b,net2) U4
an02d1 port map (a,ci,net3) U5 an02d1 port
map (b,ci,net4) U6 or03d1 port map
(net2,net3, net4,co) -- carry outend rtl
16
Agenda
1. Introduction 2. Hardware Description
Languages - Modules, Methods, Abstraction
Levels 3. VHDL - History and Standards,
Concepts of VHDL 4. Verilog - History and
Standards, Concepts of Verilog 5. EDIF - Histor
y and Standards, Levels, File Structure 6. Furthe
r languages 7. Conclusion
17
Verilog - History

• 1984 Birth of Verilog by Gateway Design
  Automation
• language roots in HiLo
• 1985 First Verilog simulator
• First extension for gate-level simulation
  Verilog-XL
• 1990 Company takeover by Cadence Design System
• 1991 Open Verilog International (OVI)
• Language Reference Manual (LRM)
• 1995 IEEE Standard 1364-1995
• 2001 Verilog 2001 with IEEE Standard 1364-2000
• Old problems have been fixed
• Simulators have been added
• Future Verilog extension for analog systems

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Verilog - Structure

• Module
• Defining signals
• Variable assignment
• Combinational elements (assign, always)
• Sequential elements (always)
• For test benches initial

module modulename (iosignallist) // Verilog
Codeendmodule
input signalnameoutput signalnamewire
signalnamereg signalname
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Verilog - Concepts

• Verilog supports
• The module and hierarchy concept
• Abstraction LevelsExplained at the already known
  example

20
Verilog - Example

• Behavioural Level
• RTL
• More detailed description necessary
• Synthesis into the Gate Netlist

module full_adder (a,b,ci,s,co) input a,b,ci
output s,co assign sabci // xor assign
co(ab)(aci)(bci)endmodule
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Verilog - Example (2)

• Gate Level
• Switch Level
• Layouting is not supported

module full_adder (a,b,ci,s,co) input a,b,ci
output s,co wire NET1, NET2, NET3, NET4
xo02d1 U1(NET1,a,b) // instantiating an XOR
gate xo02d1 U2(s,NET1,ci) // sum an02d1
U3(NET2,a,b) an02d1 U4(NET3,a,ci) an02d1
U5(NET4,b,ci) or03d1 U6(co,NET2,NET3,NET4) //
carry outendmodule
22
Comparison Verilog - VHDL

• Capability no difference
• Data types
• VHDL allows user defined types
• In Verilog only predefined types
• Design reusability
• VHDL easy referencable packages
• Verilog function access only inside a module ?
  Seperate System File
• High level constructs
• VHDL package, configuration, generate, generic
  statements
• Verilog overloading parameter constants

23
Comparison Verilog - VHDL

• Libraries
• VHDL
• Entities, architectures, packages, configurations
  in a library
• Useful for multiple design projects
• Verilog no library concept
• Test harnesses
• VHDL
• is supported by generic and configuration
  statement
• Verilog not supported

24
Agenda
1. Introduction 2. Hardware Description
Languages - Modules, Methods, Abstraction
Levels 3. VHDL - History and Standards,
Concepts of VHDL 4. Verilog - History and
Standards, Concepts of Verilog 5. EDIF - Histor
y and Standards, Levels, File Structure 6. Furthe
r languages 7. Conclusion
25
EDIF - History

• What is EDIF?
• Electronic Design Interchange Format
• History
• 1983 Initial discusses by EDIF Steering Commitee
• 1984 first EDIF specification (Version 0 8 0)
• 1986 EIA (Electronic Industries Allicance)
  supports EDIF development
• 1992 various subcommittees are reorganized into
  Electronic Information Group
• 1993 EDIF Version 3 0 0
• 1996 EDIF Version 4 0 0 (ANSI/EIA 682-1996
  Standard)

26
Levels in EDIF

• Level 0
• Only static expressions
• Level 1
• Variables
• Structures like loops or functions
• Level 2
• As mighty as a programming language (e.g. LISP)

27
EDIF File Structure

• (edif name
• (status information)
• (design where-to-find-them)
• (external reference-libraries)
• (library name
• (technology defaults)
• (cell name
• (viewmap map)
• (view type name
• (interface external)
• (contents internal)
• )
• )
• )
• )

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EDIF File Structure (2)

• (edif name
• (status information)
• (design where-to-find-them)
• (external reference-libraries)
• (library name
• (technology defaults)
• (cell name
• (viewmap map)
• (view type name
• (interface external)
• (contents internal)
• )
• )
• )
• )

• Information about
• Author name
• Modification dates
• Program versions

29
EDIF File Structure (3)
(edif name (status information) (design
where-to-find-them) (external
reference-libraries) (library name
(technology defaults) (cell name
(viewmap map) (view type name
(interface external) (contents internal)
) ) ) )

• Where to find a completed design
• Point to the top cell of a hierarchical
  description

30
EDIF File Structure (4)
(edif name (status information) (design
where-to-find-them) (external
reference-libraries) (library name
(technology defaults) (cell name
(viewmap map) (view type name
(interface external) (contents internal)
) ) ) )

• Lists external library names

31
EDIF File Structure (5)
(edif name (status information) (design
where-to-find-them) (external
reference-libraries) (library name
(technology defaults) (cell name
(viewmap map) (view type name
(interface external) (contents internal)
) ) ) )

• Stores the design
• Set of libraries contains a set of cells
• Technology stores default values (for behaviour
  or graphics)

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EDIF Cell

• An EDIF Cell consists of
• Viewmap relates to different views
• Set of views
• Interface
• Defines all input and output signals
• Contents
• Represents all gates
• Determines wiring

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EDIF Cell Example AND Gate

• (cell simplegate (cellType GENERIC)
• (view Netlist_representation (viewType NETLIST)
• (interface
• (port A (direction INPUT))
• (port B (direction INPUT))
• (port X (direction OUTPUT))
• )
• (contents
• (instance U1
• (viewRef Netlist_representation
• (cellRef an02d1 (libraryRef
  generic_gates))
• )
• )

Defines input and output signals
Gate type specification
34
EDIF Cell Example (2)
Input A

• (net A
• (joined
• (portRef A)
• (portRef A1 (instanceRef U1))
• )
• )
• (net B
• (joined
• (portRef B)
• (portRef A2 (instanceRef U1))
• )
• )
• (net X
• (joined (portRef X) (portRef Z
  (instanceRef U1)))
• )
• )
• )
• )

Input B
Output X
35
Agenda
1. Introduction 2. Hardware Description
Languages - Modules, Methods, Abstraction
Levels 3. VHDL - History and Standards,
Concepts of VHDL 4. Verilog - History and
Standards, Concepts of Verilog 5. EDIF - Histor
y and Standards, Levels, File Structure 6. Furthe
r languages 7. Conclusion
36
Further languages

• SPICE
• Circuit simulation program for analog electronics
• SystemC
• Class library for supporting system level design
• Description similar to a common HDL
• Module concept
• Supports simulation

37
Conclusion

• A lot of tools for system designers are
  available.
• Hardware Description Languages
• VHDL, Verilog
• Helpful for modelling, simulating, sythesizing
• Graphical Tools
• Can be used easily
• Future Developments
• Analog design concepts

38
References

• http//www.moxon.com/2001/11/16/channels/xml/full_
  adder/
• http//www.angelfire.com/in/rajesh52/verilogvhdl.h
  tml
• http//www.vhdl-online.de/
• Meyer, Matthias. Entwurf digitaler Systeme. 2003.
• http//www.vhdl.org/vi/comp.lang.vhdl/history.html
  
• http//www.verilog.com/
• http//www.deeps.org/verilog/veritut.html
• http//www.edif.org/introduction.html
• http//edif-tc.cs.man.ac.uk/refdemo/index.html
• http//www.doulos.com/knowhow/systemc/tutorial/int
  roduction/