Process Flow

1
Trends in development of breakthrough
technologies in 2001-2010,investment volumes for
their implementation and market capacity forecast
Investments, KK USD
2
Design rules for semiconductor products and sales
share in the world market
Market capacity ,
Power and automobile electronics 80
Industrial and military equipment 80
Consumer electronics 70
Telecommunications 60
Computer engineering 30
Mobile 10
Personal computers 10
Power and automobile electronics 20
Industrial and military equipment 20
Consumer electronics 30
Telecommunications 40
Computer engineering 70
Mobile 90
Personal computers 90
3
Life cycle of microelectronic products
Production volumes in years, x109
World tendency in the market development
depending on minimal design rules
Minimal size of element
PRODUCTION
Profitability
below 10
15-25
25-40
Sales volumes
Introduction
research, design/development
Introduction
drop
maturity
growth
Life cycle stages
2-3 years
3-5 years
1 year
1-2 years
Fundamental investigation, design and research
Equipment Technologies Products
Costs
4
What do we know about our competitors
China
Assembly IC production 10 companies (Motorola,
AMP, Fairchild, Hitachi, IRM, Lute, NEC, Samsung,
Sony, ST, Toshiba) in 6 cities (Suzhou, Shanghai,
Tiaujin, Beijing, Wuxi, Shenzhen) 1.2 kk USD in
2003, and 15.35 kk USD by 2010, that made 44 of
the world output
Started in 1990 ?200 mm 9 factories ?150 mm
10 factories ?125 mm 4 factories ?100 mm 5
factories Total 28 factories
SMIC 1300 K w/year 11 K w/year Grace 1000 K
w/year 83 K w/year Hua Hay NEC 700 K w/year 58
K w/year Otres 400 K w/year 92 K w/year Total
4100 K w/year 340 K w/year
Production volumes
5
What do we know about our competitors
RUSSIA
Joint-stock company Angstrem Manufacturing
capacities - CMOS, BiCMOS and MOS ICs with
1.5-2.0 µm design rules on 100 mm wafers,- LSI
and VLSI on CMOS and BiCMOS technologies with
0.8 - 1.2 µm design rules on 150 mm wafers.
Perspective - project FAB-2 production of ICs
with 0.25-0.35µm design rules on 200 mm wafers.
Joint-stock company Micron Manufacturing
capacities - IC on CMOS, BiCMOS and MOS
technologies with 1.5-2.0 µm design rules on 100
mm wafers Perspective - project Set up of modern
fabs for production of competitive
microelectronic products based on advanced
technologies" wafer fabs with 0.5-0.35 µm
design rules on 200 mm wafers
Estimated market capacity - 500-800 kk USD
Import ICs
Research Institution of System Analysis of the
Russian Academy of Science Research Institution
of System Analysis of the Russian Academy of
Science has the capacities for production of ICs
with 0.35 µm design rules on 150 mm wafers with
up to 500 w/month output)
Russian ICs
Domestic ICs 10-15
6-9
Integrals ICs
6
Our advantages over competitors

• orientation to development of several basic
  technological processes (CMOS, bipolar, BiCMOS)
  and not to one or two processes as usually
• clean technological module for production of ICs
  with 0.8 µm design rules
• design center (Belmicrosystems Design Center)
  equipped with modern design and development
  equipment and able to develop ICs and
  technological processes with submicron design
  rules
• reserve and experience in basic technological
  operations based on fundamental researches
• cheap skilled labor and specialists
• certification of Quality System for compliance
  with the requirements of International Standards
  ISO 9000
• cheap land and energy
• favorable tax policy

7
Problem description
Morally and physically obsolete equipment Low
efficiency
Results
Limited technological potentials Reduction of
occupied market segment
Solutions
Necessity of engineering infrastructure and clean
rooms for 0.35 µm design rules. Setting up the
production of ICs with 0.35 µm design rules.
8
Project realization

• Project constituents
• Production line modernization (engineering
  structures, clean rooms, etc.)
• Technology transfer (route, list of technological
  operations, list of equipment, technical
  requirements for VLSI design/development)
• Delivery of set of special process and check and
  measurement equipment
• Personnel training
• Production set up

9
Problems to be solved for the objective
achievement

• 1. Selection of silicon VLSI BiCMOS type with 0,5
  µm design rules.
• 2. Determination of the minimal required and
  sufficient list of technological operations.
• 3. Determination of the minimal required and
  sufficient list of special process equipment and
  check and measurement equipment.
• 4. The same items like items1,2,3, but for VLSI
  CMOS with 0,35 µm design rules.
• 5. Purchasing special process equipment and check
  and measurement equipment.
• 6. Delivery, installation and start-up of special
  process equipment and check and measurement
  equipment.
• 7. Preparation of Module 7 clean rooms.
• 8. Appraisal of Module 7
• constructions walls, ceilings, floors,
• vibrocharacterization,
• air preparation conditioners, filters, recycle
  system, inspection, control and monitoring
  system,
• water preparation DI water, recycled water,
  drinking water, etc.
• drains, cleaning system,
• gas,
• power,
• vacuum,
• Totally 20 power supply units of REM factory.
• 9. Development and implementation of basic
  technology.
• 10. Design/development and manufacture of
  products.

10
Project realization options
11
DEVELOPMENT OF NEW TECHNOLOGIES
Options Actions 1. Financial and technical
agreement 2. Technology transfer 2?. Development
of a preliminary route, list of operations, set
of equipment 4. IC design and foundry-orders for
pilot lots 3. Purchase and delivery of the
equipment set 4. Installation, start-up,
acceptance according to OEMs specification 5.
Personnel training during technological
operations 6. Development of test matrix design
and technology 7. Test matrix production
production line technological start-up 8.
Research, analysis, extraction of spice
parameters of test matrix element base 9.
Development of structure and technology of the
1st IC 10. Manufacture of engineering lot of the
1st IC 11. Research, analysis, extraction of
spice parameters of commercial IC element base,
structure and technology correction (iteration
1) 12. Manufacture of commercial IC engineering
lot 13. Commercial IC testing (3000 h) 14.
Testing at customers site (2?3000 h) 15.
Start-up of premass (mass) production
1
2
3
4
1 purchasing the technological process
description, route, design rules, spice-parameters
2 technological process preparation
3 introduction and testing
4 technological support
Loan repayment start
12
Full Process Transfer Schedule
Implementation phase
Activity
Ramp-up
Preparation phase
1. Finalization of technical annex 2.Transfer
of documentation 3.Equipment procurement 4.Per
sonnel training 5.Design of transfer vehicle
6.Validation of process steps 7.Validation
of modules 8.Full process integration
Process Acceptance 9.Transfer support
aftercare
partner
Integral
partner
Integral partner
Integral partner
Integral partner
Integral
13
EXTERNAL APPRAISAL OF THE PROJECT

• 1. Appraisal of Module 7 and Module 8 clean rooms
  and utilities made by Siemens Industrial
  Building Consultants GmbH
• the possibility of setting up the production on
  CMOS technology with 0.35 µm design rule was
  confirmed
• the complete list of works aimed at
  modernization of engineering systems, including
  the clean rooms construction, equipment and
  utilities was determined
• the cost of works for Module 7 and Module 8 was
  evaluated.
• 2. The appraisal of financial and economical
  status of State-owned enterprise Semiconductor
  devices Factory as for 01.10.2003 was made by
  Joint-stock company CONSULTAUDIT
• financial and economical status of the
  enterprise is considered to be satisfactory
• in general the enterprise is solvent and
  financially stable.

14
REQUIRED SPECIAL PROCESS EQUIPMENT
Equipment type, producer and the equipment cost
shall be clarified while signing the contract
15
REQUIRED CHECK AND MEASUREMENT EQUIPMENT
Equipment type, producer and the equipment cost
shall be clarified while signing the contract
16
Our potentials
All factories of Integral" 200 mm wafers
?200 mm 5000 wafers/month ?150 mm 7500
wafers/month ?100 mm 50000 wafers/month
Total10500 wafers/month
17
Economics

• Market of State-owned Enterprise
• Semiconductor Devices Factory
• telecommunications - 1.37 kk USD/year (India)
• watch/clock and melody IC (the year 2005) - 6-8
  kk USD/year
• calculator IC - 2-3 kk USD/year
• analog, logic ICs, microcontrollers, memory ICs
  sales activation and market expansion
• computer IC restoring the relations with the
  companies of Russian defense establishments,
  obtaining the status of independent supplier of
  specific ICs according to own technical
  specifications
• net income shall make 11 - 15 kk USD
• net profit makes 5 - 6 kk USD

18
Forecast of financial and economic activity
Project realization will allow to speed up the
turnover of floating assets of the company by 41
day. The total growth of net floating assets will
make 14845 k USD (including current activity of
the company - 275 k USD in 2004 at the cost of
the project realization in the period from 2005
till 2011 - 14507 k USD). Except the growth of
net floating capital the own funding sources are
as follows accumulated depreciation fund makes
4638 k USD and the current depreciation in 2004
makes 1158 k USD ( 204 k USD will be spent for
the project realization in 2005) . Reserve
resource of own funds for the project realization
means demand balance on bank accounts of the
company on 01.01.2004 to the sum of 42 k USD. The
sum of net income (net profit depreciation)
within the period involved will increase from
2469 k USD in 2004 up to 13110 k USD in 2001. The
project can be realized, since the sum of
accumulated money balance is positive for every
year of the project realization. The total sum of
the accumulated balance will make 17024 k USD
with the growth in 2011.
19
Schedule of the project realization
Stages of the project realisation
Mes. unit
Total
Total, Mil.
20
Project schedule Setting up a production line of
CMOS IC on 200 mm wafers with 0.5 µm design rule
(4000 wafers/month) and pilot line of CMOS IC
with 0.35 µm design rule (1000 wafers/month)
1. Technology transfer 1.1 Process flow
transfer 1.2 Equipment set transfer 1.3 Technical
documentation transfer 1.4 SPICE parameters
transfer 1.5 Design rules transfer 1.6 Training
provided by the supplier 1.7 Technology
transfer kit translation 1.8 Technology
transfer kit study
2. Equipment purchase 2.1 Contract signing 2.2
Transportation 2.3 Installation 2.4 Start up 2.5
Personnel training on operations of equipment
3. English language courses
4. Module 7 construction and upgrading 4.1
Foundation 4.2 DI water 4.3 Gases 4.4 Microclimate
5. Purchase of wafers for equipment start up
6. Purchase of spare parts 7. Selection of IC,
technical specs for design 8. Development of
technology and construction 9. Technical start up
of the process stages 10. Formation of the
blocks 11. Formation of the whole route 12. Pilot
lot start up 13. Making the reticles
21
Expenditures schedule, K
K
Years
1. Own means - total
2. Foreign loans from commercial bancs
22
Debts repayment at state -owned enterprise
semiconductor Devices Factory, K
K
Years
Primary debt sum
Interest and primary debt sum
Primary debt repayments
Loan debt
Interest and primary debt repayments
23
Questions