INTERCONNECT ISSUES for 45 nm

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INTERCONNECT ISSUES for 45 nm 32 nm TECHNOLOGY

• Dennis Buss
• Texas Instruments Inc
• buss_at_ti.com

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AGENDA

• Technology issues
• Variation in interconnect R C
• Design issues
• Contributors
• Tom Bonifield
• Chidi Chidambaram
• NS Nagaraj
• Joe McPherson

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Interconnect Trends

• The increasingly deleterious effect of metal R
  C was predicted many years ago and led to
• Cu metal _at_ 130 nm
• Low-k _at_ 90 nm
• MARCO IFC

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Interconnect Trends

• AlCu 3 µ? - cm
• Cu 2 ?? cm
• 33 improvement

SiO2 k 4.2 FSG k 3.6 130 nm OSG k 2.9 90
/ 65 nm k 2.5 45 nm k 2.2 ?
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Interconnect Trends
At 65 nm, 50 of the delay in typical dense logic
is the result of interconnect.
If we improve transistor speed by 20 and
interconnect remains unchanged overall speed
increases by 10
Performance Sensitivity Chart
Rest of intra-cell cap
Contact-to-gate cap
POLY Resistance
Transistor
Inter-cell metal
Intra-cell process innovation helps
resistance
Rest of intra-cell
resistance
Inter-cell capacitance
Contact resistance
Diffusion resistance
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90nm Metal Stack Options
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Effective Dielectric Constant

• Etch stop/barrier layers have a HUGE impact on
  Capacitance
• Higher-k materials introduced for manufacturing
  and reliability reasons
• Effective dielectric constant increases
• Examples
• 65 nm Low-k 2.9, Keff 3.31
• Increase by 14
• 45 nm Low-k 2.5, Keff 2.98
• Increase by 19
• Low-k barriers/etch stop layers will help better
  entitlement

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Interconnect Scaling Trends

• Resistance increases
• Scattering
• lost copper area due to liner
• Keff doesnt decrease fast enough
• Barriers and etch stops
• dielectric damage

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Ideal conductor _at_ 3 mOhm-cm
(Ideal Conductor means no barrier metal and
constant resistivity i.e., no scattering effects)
Ideal conductor _at_ 2 mOhm-cm
Ideal conductor _at_ 4 mOhm-cm
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Ed Burke
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Process Damage to ULK Dielectrics

• Added porosity increases the challenge of
  minimizing plasma-induced dielectric damage
• Increased k-value upon formation of more
  polarizing silanol bonds during etch/ash
• Surface and bulk silanol formation can be
  partially repaired using various silylation
  approaches
• Low-damage plasma processes and/or damage repair
  processes are critical to realizing the benefit
  of porous-ULK films

Ref SEMATECH, Semiconductor International, June
2005
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Ed Burke
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Changes Affecting Electromigration and Stress
Migration at 45nm and Beyond
Weakest interface

• JMAX is a big scaling issue
• Design improvements may not be able to overcome
• Fixes could drive new materials

Metal Cap (CoWP)
Dielectric barrier
Cu alloying
ALD barrier
Cu
Cu
Ultra-low-k dielectrics degrade EM due to low
modulus and low thermal conductivity
Microstructure control
Metal barrier
Low-k
Metal Caps for Cu, Cu Alloying and Microstructure
Control, and ALD Barriers are Possible Actions
with Risks due to New Materials and Interfaces
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Systematic Interconnect Variations
CMP
Selective Process Bias
Trench copper thickness (Etch)
Trench depth
Line width
RC Extraction
Future Direction
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An Example of Prediction of Copper Loss due to CMP
Max Delta of 250A or /-12 thickness
90nm prediction
Source Praesagus
Systematic metal thickness variation could be
predicted and should be accounted during design
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Motivation
WaferSurface

• Large Copper Thickness Variations
• Typically /- 20
• Variation Caused by Design Features
• Varying Copper Density
• Different Feature Widths Perimeters
• Long-Scale Pattern Interaction
• Copper Thickness Variation Causes R C Variation
• Timing Failures
• Decreased Performance
• Increased Power Consumption

ChipSurface
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Topographical Evolution at ECD and CMP

• ECD

Bulk CMP
Touchdown CMP
Barrier CMP
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Layout dependent variation

• Dishing
• Pad bending into large line features
• Erosion
• Oxide and metal removal in dense features

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Clock Tree Design and Interconnect Variations
Clock and data have different variations in delay
due to spatial and layout dependent effects
Limit clock routes to similar layers (say M3 and
M4) to minimize Interconnect variations
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SYSTEMATIC PREDICTABLE VARIATIONS

• Histogram of Critical Path Delays
• Each CP has a different delay error as result of
  predictable variations in capacitance.
• If the correct capacitance can be predicted, the
  buffer in each CP can be customized to the
  predicted load.
• Margin is zero.

• For systematic/predictable variations that are
• - time independent
• Independent of circuit activity
• Margin can be reduced, in principle to zero if
  variation can be predicted exactly.

• Hazard in assuming delays are statistical
• If we assume the variations in capacitance are
  statistical and target the 3? point in the
  distribution of the die will fail 100.

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Statistical Random Variations

• Probably very few of the variations in the
  manufacturing process are statistical random.
  RDF is a truly random process.
• Statistical methods may, in some cases, be used
  to reduce margin even if the variations are not
  truly random/statistical.
• Statistical methods can be used to reduce margin
  when the variation is within die, and when it is
  global.

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STATISTICAL OR RANDOM VARIATIONS

• The key concept in SSTA is to add variances in
  quadrature, not linearly.
• The industry has been using SSTA principles with
  regard to transistors

• If Id were the only statistical variable the
  optimum margin would be 3? weak models for Id

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STATISTICAL OR RANDOM VARIATIONS

• But Id is not the only statistical variable
• Metal Capacitance C
• Metal Resistance R
• Assume for simplicity
• Single level of metal
• All transistors correlated
• Ignore metal resistance

3? margin for Td is 1/ ?2 of worst case margin
(
)
2
(
)
2
? Td
? T
Var ( Td )
Var Id
Var C
? Id
? C
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Variations in Resistance are correlated to
Variations in Capacitance

Resistance vs. lateral capacitance
Resistance vs. total capacitance
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STATISTICAL VARIATIONS

• SSTA (adding variations in quadrature) works
  when the distributions are well-behaved.

Idrive

Idrive
Capacitance
Capacitance

• It clearly does not work when the distributions
  are not centered

.
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TAXONOMY OF INTERCONNECT VARIATIONS THAT AFFECT
DESIGN
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CONCLUSIONS

• Metal interconnect increasingly limiting logic
  speed
• R C are increasingly problematical
• Innovations must be sought in technology, design
  architecture
• Metal R C variations are requiring increased
  margin. R C Variations need to be addressed by
• Technology innovations to minimize variations
• Tools to predict the variation