Noise Canceling in 1D Data: Presentation

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Mar 23rd, 2005 Full chip LVS
Noise Canceling in 1-D Data Presentation 9
Seri Rahayu Abd Rauf Fatima Boujarwah Juan
Chen Liyana Mohd Sharipp Arti Thumar
M2
Project Manager Bobby Colyer
Overall Project Objective Implementing Noise
Cancellation Algorithm in Hardware
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Status

• Design proposal (Done)
• Architecture proposal (Done)
• Size Estimates and Floorplan (Done)
• Gate Level Design
• - Schematics (Done)
• To be done
• Layout (85)
• Spice simulation

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Design Decisions

• Redesigned the horizontal FP Adder to be more
  similar to vertical floorplan
• Redesign buffers ? H-tree buffer to facilitate
  abutment with other cells
• Placement of AND gates and Mirror Adders in the
  Wallace tree

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Last Weeks Floorplan
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Current Floorplan
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Old vs. New FP Multiplier (A)
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Wallace Layout (old buffers)
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Wallace layout (new buffers)
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Old vs. New FP Adder (vertical)
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FP Adder (old horizontal)
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Floating Point Adder (horizontal)
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Challenges

• Finishing up layout
• Make sure that the signal strength is sufficient
  (buffering)
• Global wiring
• Shrinking functional blocks (white space)

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Questions?