Agenda

1
Agenda

• Project Overview
• Hardware Implementation
• Software Implementation
• Administrative Report

2
Project Overview
3
Overview

• Goal
• To continue the implementation of a spread
  spectrum RF transceiver prototype for continuous,
  wireless, and CD quality audio. The prototype
  should be portable and flexible for future
  upgrades.
• The RF transceiver should be able to announce
  information of WDW attractions and allow
  short-range communication between WDW employees.

4
Required Specifications

• 2.4 GHz RF Spread Spectrum
• 16-bit Digital Audio
• 48 KHz sampling rate
• One to Many/Many to One Communication
• Versatility
• Portability with Low Power Consumption

5
Project Background

• This project is the continuation of two previous
  senior design groups.
• Initial project was to design a transceiver using
  Blue Tooth technology.
• Due to the cost and unavailability of this new
  technology, spread spectrum was chosen to replace
  Blue Tooth.
• The Second groups objective was to upgrade the
  transceiver to CD-quality audio.

6
Our Findings

• The first group successfully designed and built
  the middle PCB with the PLD and RF Transceiver
  although they were unsuccessful in their attempt
  to produce working code for the PLD.
• The second group failed in their design and
  implementation of the top board used for the
  16-bit encoding/decoding and produced less than
  adequate code for interfacing to the DSP and
  radio.

7
Overall Block Diagram
8
Hardware Implementation
9
Atmel ATF1508AS CPLD

• Provide Interface Between the Radio and the DSP
• 7.5 NS Pin to Pin Delay
• 125 MHz Operation
• 3.3 V Power
• Reprogrammable

10
PLD Findings

• Initially we were told that the PLD was
  programmed and in working order. We discovered
  that the interface to the radio was not
  operational. When we attempted to reprogram the
  PLD from the sources given to us, we concluded
  for various reasons that the source was not the
  final release but interim development code.
• Previous groups code has been evaluated
• - Code was intended to have two primary
  functions
• 1. Glue the serial ports.
• 2. Map the radio control registers to
  the DSP memory
  address space.

11
Actions Taken

• We constructed a ISP connector circuit that will
  allow us to program the PLD from a PC.
• We attempted to compile the .PLD file given to us
  by the previous group for download to the PLD.
• After extensive interaction with the Atmel
  engineers it was determined that there were too
  many errors in the code to get it in working
  order.
• Because of errors in the .PLD file, we have not
  been able to successfully create the necessary
  JEDEC file for download to the PLD.

12
ISP Circuit / Cable to PLD download
13
Intersil Prism II Radio
14
Intersil Prism II Radio Features

• 2.4 GHz
• 11Mbps Data Transfer
• 400 ft Indoor to 3700 ft Outdoor Range
• 3V, 150 mA Power
• PCMCIA Connectors

15
Intersil Prism II Radio Components

• Baseband Processor
• Controls Data from and to DSP
• Modulates/Demodulates Signals
• Spread Signal Using PN Code for Security
• MODEM
• Filters Signals
• Modulates/Demodulates Signal to IF (280MHz)
  frequency
• RF/IF Converter
• Converts signal to RF for transmission or to IF
  in receive mode
• RF Power Amplifier
• Amplifies signal
• Dual Synthesizer
• RF and IF local oscillator generator using
  digital PLL

16
Intersil Prism II Radio
17
Codec PCB Board

• TLC320AD77 Codec
• Peripheral Circuitry
• Output/Input Analog Circuitry
• Voltage Referencing capacitors
• Clocks
• Interface to DSP

18
Our Findings

• The original Codec PCB designed by the previous
  group was not functioning correctly.
• After many attempts to troubleshoot the board, we
  found that the best approach would be to design a
  new Codec PCB.

19
TI TLC320AD7716/24-Bit Stereo Audio Codec

• Features
• Primarily designed for audio applications
  requiring high-performance digital audio
  conversion
• 16-bit delta sigma stereo ADC and DAC
• 16-, 20-, or 24-bit input/output data
• Wide range of sampling rates16 kHz to 96 kHz
• 3.3-V power supply operation
• Wide variety of serial input options

20
TLC320AD77C Codec
21
Codec Functional Block Diagram
22
Timing Clocks

• 12.288 MHz Master Clock is produced by an EPSON
  oscillator
• The Master Clock determines the Sampling rate
• 48 KHz LRCLK, which is the Sampling rate
• The Clock for the serial data or SCLK is set at
  64 times the LRCLK which is 3.07 MHz
• The LRCLK and the SCLK are produced by the TI
  TAS3001 graphic equalizer

23
The TAS 3001 graphic equalizer

• Specifically designed for use with the TLC320AD77
  Codec
• Once provided with the MCLK signal, an internal
  PLL produced the LRCLK and the SCLK
• Could easily be used for a future upgrade to
  include a graphic equalizer and various stereo
  effects.

24
TAS 3001 block diagram
25
Analog Input Circuit

• Single-pole low pass antialiasing filter to
  attenuate unwanted frequencies
• High Performance
• Low Voltage Op-Amp TI TLV2362
• 2-5V Operation
• High Slew Rate
• Good common mode rejection ratio
• Low noise

26
Analog Input Circuit
27
Analog Output Circuit with Amplifier

• Eliminate high frequency noise gt80kHz
• Output of this filter provides a noninverted
  signal
• 150 mW Stereo Audio Amplifier from National
  Semiconductor Boomer headphone amplifier
• 3-5V Operation
• Low total harmonic distortion 0.025
• 2 Channels
• Completely glueless (no peripheral circuits
  needed for initializations)

28
Analog Output Circuit with Amplifier
29
Voltage referencing Capacitors
30
Specification

• 100 MIPS Execution
• 3V Power
• Includes power supply, I/O connectors, Memory,
  PCL, McBSP, and Expansion Slots.
• Interface for Baseband Processor

31
Texas Instruments DSP
32
Direct Memory Access (DMA) Controller

• Function
• Transfers data between points in memory without
  intervention by the CPU
• Features
• has six independent channels
• higher priority than CPU for both internal and
  external accesses
• each read or write transfer may be initialized by
  selected events
• on completion of a half-block or full-block
  transfer, each DMA channel may send an interrupt
  to the CPU
• provides flexible address-indexing modes for easy
  implementation of data management schemes such as
  auto buffers and circular buffers
• Derogatories
• Contrary to the stated documentation, the DMA on
  this generation DSP can only work with a small
  subset of addressable RAM.

33
Multichannel Buffered Serial Port (McBSP)

• Function
• Provides high-speed, full-duplex interface to
  other C54x devices, codecs, and other devices in
  a system
• Features
• Full-duplex communication
• Double-buffered data registers which allow a
  continuous data stream
• Independent framing and clocking for receive and
  transmit
• A wide selection of data sizes including 8-, 16-,
  20-, 24-, or 32-bits

34
Interface to the DSP
35
Software

• Networking Layer
• Audio Layer
• Issues

36
Network Interface

• Breaks network interactions into frames
• Quasi-Ethernet
• Ethernet style source/destination addressing
• Frame type field that identifies the higher level
  layer responsible for the given frame
• Optional CRC

37
Network Initialization

• The network interface is assigned a source
  address.
• Notification functions are registered for all
  application services interested in receiving
  frames.
• A pool of network buffers and TX/RX queues are
  setup in a pre-determined memory location.

38
Network Runtime

• Transmitting frames
• The application obtains a network buffer from the
  pool.
• The buffer is filled with the data to send.
• The application passes the buffer, destination
  address and frame type to the network layer which
  queues it for transmission.

39
Network Runtime

• Receiving frames
• Application services register a destination
  address and frame type tuple with the network,
  specifying a notification function.
• Whenever the receive queue for the service
  becomes non-empty, the network layer calls the
  application provided notification function.
• The notification function must initiate the
  process of reading all available frames,
  processing each and returning it the network
  buffer pool.

40
Status of Network Layer

• We were unable to make use of the RF radio. The
  physical network device driver is currently
  implemented for loopback only.
• Work was done to link the boards together with a
  cable but due to time constraints and technicle
  difficulties this could not be completed.

41
Audio Software

• The audio software is the application service
  which provides the linkage between the network
  layer and the CODEC chip.

42
Audio Transmitter

• Separates the incoming data stream from the CODEC
  into discrete frames.
• Sends the frames to the network.

43
Audio Receiver

• On the receiving side, the audio software reads
  frames from the network.
• The frames are buffered up to a cutoff point
  prior to sending to the CODEC.
• With the memory constraints of the platform and
  the high data rate, approximately ½ second of
  data can be buffered.

44
Software Issues

• There is a high level of knowledge that must be
  obtained regarding DSP and embedded programming
  prior to becoming productive on the platform.
• The development tools provided by TI are an
  extreme hindrance to productivity.
• Testing is extremely difficult due to the
  non-portable nature of the development software.

45
Software Issues

• In attempting to implement the physical cable
  between the two devices, I was unable to properly
  generate the clocks required for the operation of
  the link.

46
Audio Status

• The audio software should provide jitter
  resistance.
• It would be fairly easy to add additional signal
  processing.

47
Work Breakdown
48
Project Gantt Chart
49
Project Gantt Chart
50
Component Price List

• 2 Intersil Radio - 600/ea
• 2 Codec PCB
• 450 total for PCB layout
• 150 total for stuffing
• 50 total for components
• 3 DSP Eval Boards - 300/ea
• Total Cost 2765