Computer Architecture: Intro Beginnings

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Computer Architecture Intro Beginnings

• J. Schmalzel
• S. Mandayam

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Course

• Introduction
• Overview
• Content launch Module 1

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Structure Conduct of the Course

• Discussion v. Lecturing
• Interaction Question/Comment Ticket
• Team-learning
• In-class labs
• Out-of-class labs, readings, problems

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Introduction

• Instructors J. Schmalzel, S. Mandayam
• Course
• Digital Foundations
• Introduction to Embedded Processors
• The Embedded Development Environment
• Interfacing to the Physical World
• Hardware and Software Trade-Offs

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Course Goal

• Goal Impart knowledge of computer architecture
  to support informed decisions about the hardware,
  software, and the hardware/software trade-offs
  that underlie the computing paradigm.

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Objectives, 1

• ? Describe major functional elements of CISC,
  RISC architectures
• Perform detailed analysis and synthesis of
  combinatorial and sequential subsystems using
  schematic and/or behavioral design capture w/ sim
• Describe principles and applications of the three
  basic computing elements CPU, MEM, I/O
• Use an embedded system that includes diverse
  architectural features

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Objectives, 2

• ? Apply analytic and simulation techniques to
  predict and verify performance metrics
• ? Design an example architecture using SOTA tools
• Identify opportunities for hardware and software
  trade-offs
• (Insert your objectives here)
• ( and here)

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Digital Foundations

• The basic model of a computer system

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Central Processing Unit (CPU)

• Controls
• Executes
• Computes (Fixed- and/or Floating-Point)

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Memory

• Program store
• Data storage
• High-speed?Low-speed
• Volatile, Non-volatile
• RAM, ROM, FLASH (EEPROM)
• Fast?Slow

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Input/Output (I/O)

• Communication between CPU and outside world
• Fast?Slow
• Standardized (e.g., IEEE 802.11b)
• Parallel (IEEE 1184)?Serial (USB 2.0)

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Hierarchical View of EP and Digital Systems
Operating System HLLs
Computer Architecture
State Machines
Interface Method
Design Techniques
MSI Functions
Boolean Algebra
Gates
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Number Systems

• Binary
• Hexadecimal
• Octal

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• For an n-bit binary number
• Base notation. For a k-bit binary number with
  n-bits to the left of the radix point and m-bits
  to the right of the radix point.
• For example, 1101001.101 ______________10
• (64 32 8 1) . (0.5 0.125)
• 105.625
• Similarly, for hex

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Conversions
11111111 ? ____________(10) (Fast way 100000000
-1 255) 10101010.01 ? _____________
(10) (AA.416 1016 10 .25 170.25) AB6C.D
? _________________________ (2) ?
___________(10) (1010101101101100.1101 104096
11256 616 12 13/16 43,884.8125)
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Coding

• Binary system must be used to accomplish many
  functions such as arithmetic and data
  transmission. A code defines the mapping between
  binary digits and the intended application.

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Example Codes

• Gray code Only one bit change between adjacent
  codes (000?010?110?100 ?101?111?011?001?000)
• Binary-Coded Decimal (BCD) Direct (but
  inefficient) coding of decimal numbers using 4
  bits

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2s Complement
Need A method to represent negative numbers. Can
use a sign bit magnitude e.g., 5 0 101, -5
1 101, but there are better codes. The 2s
Complement is one. 1s Complement Complement
each bit. 1s Complement of 11011 is 00100 2s
complement 1s complement 1 Example Find 2s
complement of 1001100. ? _______________
(0110100.) To check, sum of the positive and
negative codes should sum to zero (ignore
overflow out of msb). (By inspection trick
Working from right to left, write down all zeros
until the first 1. Write it down, too, then
complement every bit after that.)
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Boolean Algebra

• True/False
• High/Low
• On/Off
• 5 Vdc / 0 Vdc (3.3 Vdc / 0 Vdc)
• Notation
• Variable by itself is assumed true
• Variable with a symbol denotes complementation
  /

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Boolean Identities

• X?00
• X?1X
• X?XX
• X?X0
• X0X
• X11
• XXX
• XX1
• XX

• Commutative Laws
• XYYX
• XYYX
• Associative Laws
• X(YZ)(XY)Z
• X(YZ)(XY)Z
• Distributive Laws X(YZ)XYXZ
• DeMorgans Theorems
• (X?Y)XY (XY)X ?Y

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Gates (p. 63 MK)
AND ( C ) OR ( ? C ) NOT
Inverter ( / C ) XOR ( ? C ?
) NAND NOR XNOR
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Combinatorial Design Process

• Problem statement
• Truth table and describing Boolean Algebra
• Simplification
• Implementation
• Verification

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Design Examples

• Full Adder (Step 1 Design a device that performs
  binary addition, including carry input.)

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Full Adder Truth Table (Step 2)
Sum-of-Product Boolean expressions for S and
Co S CiAB CiAB CiAB CiAB Co
CiAB CiAB CiAB CiAB
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Graphical Simplification (Step 3)
Ci
A Karnaugh-Map organizes truth table entries as a
gray code--only one variable changes between
adjacent cells. This lets you use the identities
XX1 and X1X to simplify by inspection. For
example, the AB subcube ABCi ABCi
AB(CiCi) AB(1) AB
Co
0
1
0
0
00
BCi
1
01
0
AB
AB
11
1
1
ACi
0
10
1
Co AB ACi BCi
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Other Simplification Methods

• Quine-McCluskey algorithm
• Espresso
• http//www-cad.eecs.berkeley.edu80/Software/softw
  are.html
• http//cse.bellarmine.edu/espresso (C. Staley
  Find it on download.com)

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Espresso Demo
Simplify So and Co for FA
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Implementation (Step 3)
Translate the simplified BA to a network of gates
Ci
A
Ci
Co
B
A
B
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Verification (Step 4)
Verify the proper behavior of the design. Use
simulation techniques to present test vectors and
compare responses to predictions. Exhaustive v. S
tatistical (Monte Carlo)
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Combinatorial Function Blocks

• Decoders
• Multiplexers

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Digital Foundations, cont.

• The basic model of a computer system

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Real Gates

• Logic levels are voltage levels
• Finite current drive
• Timing diagrams
• Finite switching speed
• Propagation delays
• Noise

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Logic Levels are Voltage Levels
Vdd
High
VOHtyp
VOHmin
VIHmin
VILmax
VOLmax
Vss
Low
VOLtyp
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Finite Current Levels
The electrical circuit model for a digital output
(or input) includes a series impedance. This
helps explain why a gate cant source/sink
unlimited amounts of current (mA v. A).
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Finite Switching Speeds
Example Switching speed of an inverter. A timing
diagram shows behavior as it develops with time.
Input (Ideal)
Output
tr
tf
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Finite Propagation Delays
Example Switching speed of an inverter.
Input (Ideal)
Output
tPDLH
tPDHL
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Noise
How well logic is able to reject noise is
described by its Noise Immunity. The Noise Margin
(NM) is the predicted ability of a device to
handle noise on its inputs and still reliably
determine the correct logic levels. NML VOLmax
- VILmax NMH VOHmin - VIHmin
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Logic Levels/Voltage Levels for 74HC138 w/ VCC5
Vdc
_at_IOH -20?A
Vdd
High
VOHtyp
4.999
VOHmin
4.9 V (5.0-0.1)
VIHmin
3.5 V (0.75.0)
VILmax
1.5 V (0.35.0)
VOLmax
0.1 V (0.00.1)
Vss
Low
VOLtyp
_at_IOL 20?A
0.001
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Variation in VOH and VOL
IOH
Rs
VOH or VOL
Ideal VOH or VOL

IOL
This is reference direction--thats why IOH is
negative.
What is a typical Rs?
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Calculation of Rs at IOL of 4 mA
IOH
Rs
VOH or VOL
Ideal VOH or VOL

IOL
This is reference direction--thats why IOH is
negative.
Use 6 Vdc values 0.26V/.004A
65 ?
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Propagation delay (6 Vdc)

• From A, B, or C to any Y output Max 38 ns
• From Enable to any Y output Max 33 ns

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Questions, Comments, Discussion