Combinational Logic IV Programmable Logic Devices

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Combinational Logic IVProgrammable Logic Devices

• Instructor Koling Chang
• email kchang_at_cs.ucdavis.edu

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Outline

• Programmable Logic Device (PLD)
• ROM
• PROM/EPROM
• Programmable Logic Arrays (PLA)
• Programmable Array of Logic (PAL)
• Complex PLD (CPLD)
• Field Programmable Gate Array (FPGA)

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ROM

• Read-Only Memory
• Outputs are data, inputs are addresses.
• Outputs are solely based on the inputs.
• Can be implemented using combinational logic.
• Usually implemented using generic logic arrays.
• In practice, they are programmable. (EPROM)
• Data remain after power cycles.

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ROM (cont.)

• Read-only memory with n inputs and m ouputs

n output variables
n input variables
100.110 010.111 101101 110010 . . . 001011 11
0110 011000 111101
0000 0001 0010 0011 . . . 1100 1101 1110 11
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ROM 2n words x m bits
n input lines
m output lines
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ROM (cont.)

• ROM implemented by an Decoder and an Array

DECODER
MEMORY ARRAY
n inputs
2n decoded lines
m outputs
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An 8-word x 4-bit ROM

• F0 S 0,1,4,6 AB AC
• F1 S 2,3,4,6,7 BAC
• F2 S 0,1,2,6 ABBC
• F3 S 2,3,5,6,7 AC B

F0 F1 F2 F3
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PROM/EPROM

• ROM
• Programmed at IC manufacturing phase
• Programmable ROM
• Programmable at development phase by blowing
  fusible links
• Erasable Programmable ROM
• Programmable at development phase and erasable by
  ultraviolet

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ROM (cont.)

• Combinational logic can be designed using the
  device similar to programmable ROM.
• PLA
• PAL
• FPGA

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Programmable Logic Arrays (PLA)

• PLAs
• Implement sum-of-product expressions
• No need to simplify the logical expressions
• Take N inputs and produce M outputs
• Each input represents a logical variable
• Each output represents a logical function output
• Internally uses
• An AND array
• Each AND gate receives 2N inputs
• N inputs and their complements
• An OR array

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Programmable Logic Arrays (cont.)

• A blank PLA with 2 inputs and 2 outputs

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Programmable Logic Arrays (cont.)

• Implementation examples

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Programmable Logic Arrays (cont.)

• Simplified notation

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Programmable Array Logic Devices

• Problem with PLAs
• Flexible but expensive
• Example
• 12 X 12 PLA with
• 50-gate AND array
• 12-gate OR array
• Requires 1800 fuses
• 24 X 50 1200 fuses for the AND array
• 50 X 12 600 fuses for the OR array
• PALs reduce this complexity by using fixed OR
  connections
• Reduces flexibility compared PLAs

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Programmable Array Logic Devices (cont.)

Notice the fixed OR array connections
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Programmable Array Logic Devices (cont.)

• Terms cant be shared among outputs, no need to
  maximize common terms.
• Limit of terms can be eased by feedback lines.

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Programmable Array Logic Devices (cont.)

• An example PAL (Texas Instruments
  TIBPAL22V10-10C)
• 22 X 10 PAL (24-pin DIP package)
• 120-gate AND array
• 10-gate OR array
• 44 X 120 5280 fuses
• Just for the AND array
• OR array does not use any fuses
• Uses variable number of connections for the OR
  gates
• Two each of 8-, 10-, 12-, 14-, and 16-input OR
  gates
• Uses internal feedback through a programmable
  output cell

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Programmable Array Logic Devices (cont.)

• MUX selects the input
• S0 and S1 are programmed through fuses F0 and F1

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PAL Example

• Cypress C22V10D

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CPLD

• To get more gates
• Put several PALs on a chip.
• Put programmable interconnect matrix between
  them.
• Complex PLD

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CPLD Example

• Cypress CY37128

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FPGA

• Field Programmable Gate Array
• Put lots of primitive logic elements in an array
  with programmable routing among them.
• Primitive Elements
• an NAND gate
• A 2/1 mux (this happens to be a complete logic
  family)
• A Lookup table (nx1)
• Often combine one of the above with a D-FF to
  form the primitive.

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FPGA Example

• Altera FLEX 10K

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FPGA Example (cont.)
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Design Flow

• In old days, logic are manually analyzed and
  programmed onto PAL devices.
• In modern days, logic compiler can take schematic
  and/or hardware description language designs and
  generate outputs for fitters to place and route
  the design onto targeted devices.
• CAD Vendors Synopsys, Aldec (Xilinx Foundation),
  Mentor, Cadence, Viewlogic,