Lecture Overview

1
Lecture Overview

• Six addressing Modes immediate, direct,
  extended, index, inherent, relative.
• Instructions
• Machine code/language
• Test and logical instructions
• Branching and looping in assembly programs
• Time delays in assembly programs
• Simple assembly program

2
What are addressing modes?

• Addressing modes tells the CPU how to obtain
  data.
• Addressing modes provides programmer with various
  ways of handling data to speed up processing
• Efficient use of addressing mode can help
  reducing number of instructions in a programs
• Each of the addressing modes (except immediate
  and inherent) results in an internally generated
  16 bit value referred to as the effective address

3
Addressing modes cont

• M68HC11 has six addressing modes
• Immediate
• Direct
• Extended
• Index (with either of two 16 bit index registers
  and an 8 bit offset)
• Inherent
• Relative

4
Immediate Mode (IMM)

• Data is part of the instruction
• Immediate addressing mode is specified by the
  character which precedes the data
• Examples
• LDAA 22 - loads value 22 into accumulator A
• ADDA _at_32 - adds the octal value 32 to
  accumulator A
• LDX 1000 - loads the hex value 1000 into the
  index register X

5
Direct Mode (DIR)

• In the direct mode the least significant byte of
  the effective address appears in the instruction
• Higher order byte is assumed to be 00 by CPU
• Direct mode limits the addressing range from
  0000 to 00FF
• Example
• ADDA 21 - Adds the value stored in location
  0021 to acc A
• SUBA 08 - Subtracts the value stored in 0008
  from acc A
• The advantage is that this form of addressing is
  faster than its equivalent in extended mode ( by
  one clock cycle)

6
Extended Mode (EXT)

• In the extended mode the full 2 bytes of
  effective address is part of the instruction.
• This explicit appearance of the address enables
  access to the complete range 0000 -FFFF
• Example
• ADDA 0001 - Adds the value stored in location
  0001 to acc A (Compare to DIR mode - note would
  use former mode in this example)
• SUBA 8008 - Subtracts the value stored in 8008
  from acc A
• LDX 1000 - Loads a 16 bit value into index
  register X - note upper byte from 1000 and lower
  byte of X from 1001.

7
Indexed Mode (INDX, INDY)

• In this mode one of the index registers (IX or
  IY) is used in calculating the effective address
• Base address is stored in IX or IY and 8-bit
  offset is used as part of the instruction
• Offset range is from 0-255
• If no offset is specified, assembler assumes
  zero
• Offset is added to base address to calculate the
  effective address
• Example
• ADDA 10,X - adds the value stored at the memory
  location pointed to by the sum of 10 and the
  contents of the index register X to Acc A. eg X
  contains 8000 then contents of location 8010

8
Indexed Mode ..cont

• If Memory locations 9000 -9008 contain the
  values 15, 21, 11, 23, 31, 12, 0, 3, 56
  respectively and index register X contains 9000
  then what value is added to Acc A in the
  following instructions
• ADDA 07,X
• ADDA 05, X
• Useful mode for accessing an address which
  changes as the program runs because you can
  change the contents of the index registers as the
  program runs.
• Very useful for accessing arrays of data
  particularly within a loop.

9
Inherent Mode (INH)

• In this mode instruction is self-contained
• Operands are CPU registers
• No additional information or data is needed from
  memory
• Example
• ABA - adds contents of accumulator B to
  accumulator A.
• INCB - increments the value of accumulator B by 1
• Note this mode is characterized by single
  instruction where the operations are inherently
  performed.

10
Relative Mode (REL)

• Relative mode is used only for branch
  instructions.
• Branch instructions use an offset (signed byte)
  which indicates the distance of branch address
  relative to PC
• Offset range is from -128 to 127
• When the branch condition is true, the offset is
  added to the program counter to form the
  effective branch address.
• Example
• BCC 05

11
68HC11 Instructions
LOAD instructions transfers data from memory to
register LDD ltoprgt D ? M M1 LDX
ltoprgt IXH ? M , IXL ? M1 LDY
ltoprgt LDS ltoprgt SPH ? M , SPL ?
M1 ltoprgt can be immediate, direct,
extended, or index mode Examples LDD
10 LDX 1000
12
ADD instruction performs addition ABA A ?
AB ADDA ltoprgt A ? AM or A ?
Avalue ADDB ltoprgt A ? BM or B ?
Bvalue ADDD ltoprgt D ? DMM1 or D ?
Dvalue(16-bit) ltoprgt is specified using
immediate, direct, extended, or index
mode Examples. ADDA 10 A ? A10 ADDA
20 A ? A0020 ADDD 30 D ?
D00300031
13
SUB instruction performs subtraction SBA A ?
A-B SUBA ltoprgt A ? A-M or val SUBB
ltoprgt B ? B-M or val SUBD ltoprgt D ?
D-MM1 or val SBCA ltoprgt A ? A M
C flag SBCB ltoprgt A ? B M C
flag ltoprgt can be immediate, direct,
extended, or index mode Examples SUBA
10 SUBA 10 SUBA 0,X SUBD 10,X
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STORE instruction stores values/address onto
memory STAA ltaddrgt M ? A STAB ltaddrgt M ?
B STD ltaddrgt MM1 ? D STX ltaddrgt M ?
IXH , M1 ? IXL STY ltaddrgt STS
ltaddrgt ltaddrgt can be direct, extended, or
index mode Examples STAA 20 STAA
10,X STD 10 STD 1000 STD 0,X
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Increment/decrement instruction performs
increment or decrement

• INCA A ? A01
• INCB B ? B01
• INC ltaddrgt M ? M01
• DECA A ? A-01
• DECB B ? B-01
• DEC ltaddrgt M ? M-01
• Example
• LDAA 10
• INCA
• DECA

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68HC11 Machine Code A 68HC11 instruction
consists of 1 to 2 bytes of opcode and 0 to 3
bytes of operand information Examples Ma
chine instructions High-level Assembly
instruction (in hex format) language
statements I29 LDAA 29
86 1D LIM STAA 00
97 00 (Assume I, L, M ADDA 02
9B 02 refer to
memory STAA 01 97
01 locations 00, 01, 02)

17
Decoding machine language instructions Note this
is more difficult than assembling machine
code Sometimes you need to re-engineer
someones program to determine its operation but
you can only access the machine code. Thus you
have to disassemble the machine
code. Procedure Step 1 Compare the first one or
two bytes with the opcode table to identify the
corresponding assembly mnemonic and
format. Step 2 Identify the operand bytes after
the opcode field. Step 3 Write down the
corresponding assembly instruction. Step 4
Repeat step 1 to 3 until the machine code file
is exhausted.
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Examples of assembly instructions and their
machine code

• machine code assembly instruction format
• 01 NOP
• 86 LDAA IMM
• 96 LDAA DIR
• C6 LDAB IMM
• D6 LDAB DIR
• CC LDD IMM
• DC LDD DIR
• 8B ADDA IMM
• 9B ADDA DIR
• CB ADDB IMM
• DB ADDB DIR
• C3 ADDD IMM
• D3 ADDD DIR
• 97 STAA DIR
• D7 STAB DIR
• DD STD DIR

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Test operation

• Allow CPU to test signed values for positive,
  negative or zero values
• Subtracts 00 either from memory location or
  accumulator A or B
• Sets or clears flag bits N or Z
• Instructions are
• TST test memory location
• TSTA test accumulator A
• TSTB test accumulator B

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Test operation Example

• TST 1003 1003 is the address of port
• C of MCU
• If the value in port C is
• Positive value N0 Z0
• Negative value N1 Z0
• Zero value N0 Z1

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Logical operations

• Boolean operations are
• AND
• OR
• XOR (Exclusive OR)
• 1s complement

22
Logical Operation

• AND operation is used to perform masking
• ANDing 0s with any other bits will result in 0s
  in certain bits of a byte called Masking
• e.g.
• 1 1 1 1 1 1 1 1
• 1 1 0 0 0 0 1 1
• 1 1 0 0 0 0 1 1

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Logical cont

• AND instructions are
• ANDA A? A ? val
• ANDB B? B ? mem
• e.g. e.g.
• ANDA 0F ANDB D330
• 0 0 0 0 1 1 1 1 0F
• 1 1 1 1 0 0 0 0 ? A
• A ? 0 0 0 0 0 0 0 0

24
Logical cont

• OR instructions are
• ORAA A? A ? mem
• ORAB B? B ? mem
• e.g.
• ORAA D330
• 0 0 0 0 1 1 1 1 ? D330
• 1 1 1 1 1 1 1 1 ? A
• A ? 0 0 0 0 1 1 1 1

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Logical cont

• XOR instructions
• EORA A ? A? mem
• EORB B ? B ? mem
• e.g.
• EORA 5330
• 0 0 1 0 1 1 1 1 ? 2F
• 0 0 0 1 1 1 0 0 ? 1C
• 0 0 1 1 0 0 1 1 xor result

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Logical cont

• Complement
• Complement instructions
• COM
• COMA
• COMB
• e.g.
• COM D550

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Branching and looping

• Branch instruction can be used to control program
  flow
• Branch instructions use an offset address of
  range 128 to 127
• If branch is taken, offset address is added to PC
• Branch instructions two major groups
• Conditional branch
• Unconditional branch

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Conditional Branch

• Conditional branches test a flag bit in the
  condition code register
• If the condition is true, branch is taken
• Conditional branch instructions are
• BCC branch if C0
• BCS branch if C1
• BEQ branch if Z1
• BNE branch if Z0
• BMI branch if minus i.e.N1
• BPL branch if plus i.e.N0

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Conditional branch cont

• Example If agtb then do x34 else do 38 and
  store the
• result at location D110
• LDAA 0A
• SUBA D120
• BNE LABEL1
• LDAA 03
• LDAB 04
• MUL
• STD D110
• SWI
• LABEL1 LDAA 03
• LDAB 08
• MUL
• STD D110
• SWI

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Unconditional branch

• Jump and branch always instructions are referred
  to as unconditional branches.
• JMP
• BRA
• e.g. BRA Label
• e.g. JMP 19

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Looping

• Using conditional or unconditional instructions,
  it is possible to create programs loops
• Loops are useful to do repeating tasks
• e.g. for i1 to 10
• x 5i
• e.g. For i 1 to 100
• sumsumi

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Loops cont

• Example
• LDAA 0A
• LDAB 0A
• Loop MUL
• DECB
• BNE Loop
• STD D550

33
Time delay

• Time delay is very important for
  microprocessor-based system applications
• Time delays can be performed by using loops or by
  using a NOP (No operation) instruction
• Time delay using NOP
• NOP instruction does not change any CCR bits
• Adds two clock cycle time delay

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Time delay cont.

• Conditional branch instructions can be used to do
  time delay for a specified period of time
• e.g.
• LDAB count-value load B with count value
• Delay DECB 1 ?s
• BNE delay 1.5 ?s

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Time delay cont..

• Time delay can be calculated for 2MHz processor
  as

36
Multiplication

• HC11 provides one multiply and two division
  operations
• MUL dos multiplication operation
• Operands must be loaded into accumulator A and B
• Result is stored in register D

37
Multiplication cont

• e.g. LDAA 03
• LDAB 04
• MUL D ? AxB
• STD 1050

38
Tutorial 1

• 1. What do you understand by an 8-bit processor?
• 2. What is the function of program counter?
• 3. Consider the following instructions
• 00 49 JMP 009D
• 00 4A next instruction
• What is the content of PC after execution of the
  instruction?
• 4. What is a stack?
• 5. Consider the following instructions
• 00 49 JSR 009A
• 00 4A next instruction
• The stack starts at address 005A. What is the
  content of SP after execution of the
  instructions?