Quasi-adiabatic Clocking and Thermal Effect in Quantum-dot Cellular Automata

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Homework

• Your task is to design a regular structure such
  as Kronecker Lattice or Shannon Lattice using
  modern Quantum Dot Cellular Automata technology.
• Next slides show several example of such
  circuits. Please observe and understand in
  practical use the wire, the wire of inverters,
  the intersection, the fan-out, the way of
  creating inverters.
• These slides are shown to make you sensitive to
  several problems that may occur in practical
  circuit designs.

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Majority Gate and its uses to realize AND and OR
gates.
Smaller inverters will be also shown
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Majority Gate
Look also to lecture notes for explanation how
this gate works
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Coplanar wire-crossing
Inverter chain goes vertically
Normal array goes horizontally
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Inverter
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Realization of a circuit
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This slide shows how you can use PowerPoint to
create well-aligned to grid figures of wires and
intersection of wires.
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Homework Continued

• Your task is to design a regular structure such
  as Kronecker Lattice or Shannon Lattice using
  modern Quantum Dot Cellular Automata technology.
• Next slide show an example of such circuit.
  Please observe and understand in practical use
  the wire, the wire of inverters, the
  intersection, the fan-out, the way of creating
  inverters.
• Please observe the small shift between the left
  and right part of the schematics. Explain why it
  is done.

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Shifted down by half cell. Explain why?
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In this and next slides we give few examples of
QD circuits to show how typical layout/logic
problems are solved.
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S1 S0
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D Filp-Flop
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Barrel Shifter
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output
Input 1
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Input 2
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control
Blue circles represent parts of wires that may be
removed or not, depending on the function that is
realized
Majority configured to OR
This slide shows Shannon cell from a Lattice.
Dimensions are wrong. Please explain how this
works and improve the wiring sizes.
Majority configured to AND
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• The next slide shows the layout of connections to
  the cell in the 33 lattice.
• It has not all power of connecting from the
  recent paper.
• Think how to modify this circuit so that there
  will be possible to connections to left, two
  connections to top and two connections to right
  cells. (in a notation where circuit grows from
  bottom to top, here the circuit grows from left
  to right).

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cell
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Simplified and non-optimized Positive Davio Cell.
Observe how EXOR is realized. Can you find a
better way?
cntr
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This is Positive Davio Cell without connections
to neighbors. The rules of neighborhood are not
preserved. Correct this circuit and try to
optimize it.
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exor
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• Next slide shows a general cell of reconfigurable
  FPGA with AND/EXOR cell. This cell can realize
  Positive and Negative Davio and Shannon (using
  exor). It allows for swapped expansions and for
  function A B XOR A B where A denotes
  arbitrary polarity of singal A.
• In the next slides inverters were not correctly
  realized. Think how this can be improved. There
  are two ways to realize inverters. Stand-alone
  and in wires.

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cntr
1
0
1
0
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Final Homework

• Select on of the following and realize preserving
  all design rules.
• A) Shannon Cell for 22 lattice
• B) Positive Davio Cell for 22 lattice
• C) General Cell for 22 lattice
• D) General Cell for 33 lattice
• E) General Cell for the paper with Mishchenko.