The CPU and Memory

1
Lecture 6
ITEC 1000 Introduction to Information Technology

• The CPU and Memory

Pitxot, Antoni Figures of the Allegory of
Memory 1981Oil on canvas180.30 x 90.40 cm.
TEATRE-MUSEU DALI
Prof. Peter Khaiter
http//www.salvador-dali.org/dali/coleccio
2
Lecture Template

• CPU
• Registers
• Register operations
• Memory implementation
• Computer Buses
• Instructions
• Using the Stacks
• Multiple Data Instructions

3
Computer unit
CPU
Highest Address Memory Lowest Address
ALU
Input/outputinterface
Control unit Program counter

• Memory is separated from the CPU

4
Components of the CPU (1 of 2)

• ALU (arithmetic logic unit)
• Performs arithmetic and logic operations (data
  changed)
• Arithmetic add, subtract, multiply, divide, etc.
• Logic AND, OR, NOT, Shift, etc.
• Data held temporary
• CU (control unit) functions
• performs fetch/execute cycle
• Accesses and retrieves program instructions from
  the memory and issues commands to the ALU
• Moves data to and from CPU registers and other
  hardware components (no change in data)
• Registers
• Example Program counter (PC) or instruction
  pointer determines next instruction for execution

5
Components of the CU (2 of 2)

• Program counter (instruction pointer)
• Contains the address of the current or next
  instruction
• Normally instructions are executed sequentially
• Memory management unit
• Supervises fetching of instructions and data from
  memory
• I/O Interface
• Provides mechanism for input/output of data
• sometimes combined with memory management unit in
  a single Bus Interface Unit

6
Concept of Registers

• Single storage locations within the CPU used for
  a particular purpose
• Used to hold a binary value temporarily
• Manipulated directly by the Control Unit
• Each register is wired within the CPU directly
  (no address needed) for specific function
• Size in bits or bytes (not MB like memory)
• Can hold data, an address or an instruction

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Registers what they do

• Hold data being processed
• Hold instruction being executed
• Memory or I/O address being accessed
• Keep status of the computer
• Conditional branch instructions

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General-Purpose Registers

• User-visible registers
• Part of ALU
• Accumulators
• Typically several dozen in modern CPUs (R0, R1,)
• Hold data of arithmetic operations
• Hold intermediate results or data values, e.g.,
  loop counters
• To transfer data between different memory
  locations and between I/0 and memory

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Special-Purpose Registers

• Part of CU
• Program Counter Register (PC) (instruction
  pointer)
• Holds address of the currently executed
  instruction
• Instruction Register (IR)
• Holds the actual instruction being executed
• Memory Address Register (MAR)
• Holds the address of a memory location
• Memory Data Register (MDR)
• Holds the actual data value from location
  specified in MAR
• Flags (one-bit register) to track special
  conditions like arithmetic carry and overflow,
  power failure, internal computer error
• Status Registers
• Several flag registers grouped together

10
Register Operations

• Load values from other locations (registers and
  memory)
• Destroys (erases) previous value in destination
• Source register (or memory location) unchangeable
• Addition and subtraction
• Result stored in the register
• Shift or rotate (left or right) data
• Test contents for conditions
• zero
• Positive/negative
• To large

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Program Counter ( PC )
A dedicated register in the CPU Contains the
address in memory of the current instruction
being executed. Incremented automatically after
each instruction. May be forced to change e.g.
jump instruction. Usually initialized to zero
when machine starts, or is reset.
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Instruction Register ( IR )
A dedicated register in the CPU which contains
the actual current instruction.
Op Code Address
What To Do
Location of Data
1101 101101100100
Simple 16-bit example
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Accumulator
A dedicated register (or set of registers) in the
CPU used for the actual manipulation of data
Default source (or destination)
register Usually contains results of arithmetic
or logical operations
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Operation of Memory

• Each memory location has a unique address
• Address from an instruction is copied to the MAR
  which finds the location in memory
• CPU determines if it is a store or retrieval
• Transfer takes place between the MDR and memory
• MDR is a two way register

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MAR and MDR
Memory Address Register (MAR) Contains Address
in memory to find or place data Memory Data
Register (MDR) Contains Actual Data to be
placed in location given in MAR, or which has
been retrieved from location given in MAR
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Generic CPU With Registers
Program Counter ( PC )
Memory
Instruction Register ( IR )
Memory Address Register ( MAR )
Memory Data Register ( MDR )
Accumulator ( A or Acc )
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MAR, MDR and Memory
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MAR-MDR Example
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Individual Memory Cell
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Memory Capacity

• Determined by two factors
• 1. Number of bits in the MAR
• 2K where K width of the MAR register in bits
• 4 bits allow 16 locations
• 8 bits allow 256 locations
• 32 bits allow 4,294,967,296 or 4 GB
• 2. Size of each memory location, m
• Memory capacity is the product
• m x 2K
• Typical values
• k 16, 17, 18, 19, 20, 21, 22, etc.
• m 8, 16, 32, 64

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Memory Implementation

• Magnetic core (1949/51 late 1960s/early 1970s
• Random Access Memory (RAM)
• Read Only Memory (ROM)
• EEPROM
• Flash ROM
• Volatile
• Nonvolatile

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RAM Random Access Memory

• Random any piece of data can be accessed in a
  constant time regardless of physical location
  (unlike tapes, magnetic or optical discs)
• Difference in technical design
• DRAM (Dynamic RAM)
• Most common, cheap
• Volatile must be refreshed (recharged with
  power) 1000s of times each second
• SRAM (static RAM)
• Faster to access than DRAM and more expensive
  than DRAM
• Volatile
• small amount used in cache memory for high-speed
  access

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RAM Sample
DRAM modules used as primary memory in PCs,
workstations, servers.
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ROM - Read Only Memory

• Implemented in early stored-program computers
  (e.g., ENIAC, after 1948)
• If write protected, becomes read-only memory
• Non-volatile memory
• to hold built-in software that is not expected to
  change over the life of the computer (e.g.,
  initial program that runs computer)
• BIOS initial boot instructions and diagnostics
• Data are physically encoded into chips
• EEPROM
• Electrically Erasable Programmable ROM
• Can be erased and reprogrammed, 1 byte at a time
  (up to 1000 times)
• Slower and less flexible than Flash ROM
• Flash ROM
• Modern type of EEPROM (invented in 1984), faster
  (erase and write in blocks of bytes)
• Higher endurance (up to 1,000,000 cycles)
• E.g., USB Flash Drives

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ROM Sample
First erasable ROM, Intel 1702 erase window in
the middle
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Memory Maps

• The usage of memory space on a system is commonly
  depicted in a memory map
• The height of the map is determined by the number
  of addresses
• The width of the map is usually 8 bits
• E.g.,
• a system with a capacity of 216 bytes

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Memory Map Sample 1
7 6 5 4 3 2 1 0
FFFF 0002 0001 0000
Data bitposition
The bottom of memory
Hexadecimaladdress
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Use of Memory Maps

• Memory maps are usually drawn to show what is
  where on a system
• what can be
• RAM, ROM, I/O, empty space
• Where
• Determined by the starting/ending addresses for
  each block of RAM, ROM, I/O,,
• E.g.,
• a memory map for a system with a capacity of 224
  bytes with two 1 MB RAM modules residing
  consecutively at the bottom of memory.

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Memory Map Sample 2
FFFFFF 200000 1FFFFF 100000 0FFFFF 000
000
14 MB empty
224 bytes 16 MB capacity
1 MB RAM
1 MB RAM
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Memory Space Exercise 1
Q A system with a memory capacity of 128 GB has
four 32 MB memory modules installed. The rest of
the memory is unused. How much memory space is
available for future expansion? (Give your answer
in decimal in megabytes.) A ?
Skip answer
Answer
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Memory Space Exercise 1
Answer
Q A system with a memory capacity of 128 GB has
four 32 MB memory modules installed. The rest of
the memory is unused. How much memory space is
available for future expansion? (Give your answer
in decimal in megabytes.) A 128 GB 4 x 32 MB
27 x 210 MB - 22 x 25 MB (217 27) MB
(131,072 128) MB 130,944 MB ?
210 127.875 GB
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Memory Space Exercise 2

• Draw a memory map for a system with a capacity of
  2 GB. Assume the system has three 32 MB memory
  modules residing consecutively at the bottom of
  memory. Illustrate the size of each block in MB
  and the starting and ending address of each block
  of memory in hexadecimal.

Skip answer
Answer
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Memory Space Exercise 2
Answer
7FFFFFFF 06000000 05FFFFFF 04000000 03FFFF
FF 02000000 01FFFFFF 00000000
1,952 MB empty
231 bytes 2 GB capacity
32 MB RAM
32 MB RAM
Note2 GB 2,048 MB
32 MB RAM
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Fetch-Execute Cycle

• Two-step process because both instructions and
  data are in memory
• Fetch
• Decode or find instruction, load the code of the
  instruction from memory
• Execute
• Performs operation that instruction requires
• Move/transform data

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Fetch-part of the Cycle

• The value in the PC (program counter) register is
  the address of the memory location that holds
  instruction to be executed
• First step is always transfer (copy) the value
  in the PC to the MAR
• Then computer can retrieve the instruction
  located at that address and place it in the MDR
• PC MAR (step 1)
• Memory MDR
• Next step transfer instruction to the IR
• MDR IR (step 2)
• Remaining steps instruction dependent

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Load Instruction

• Next step the address part of the instruction
  located in the IR is copied and placed in the MAR
• Computer retrieves actual data located at the
  address in memory and places it in the MDR
• IR address MAR (step 3)
• Memory MDR
• Next step MDR copies data to the accumulator
  register
• MDR A (step 4)
• Last step PC is incremented
• PC 1 PC (step 5)

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Load Accumulator Sample (1 of 12)
Task Simple Eight bit system. Thirty-two
memory locations (0 to 31). Load instruction
is 010. Value in location 15 is ten (i.e.
binary 00001010) PC is at 5, about to
increment. The instruction, 01001111, is in
location 6.
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Load Accumulator Sample (2 of 12)
CPU Before PC increments
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00101
IR (previous)
MAR (previous)
MDR (previous)
A (previous)
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Load Accumulator Sample (3 of 12)
Increment PC PC PC 1
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR (previous)
MAR (previous)
MDR (previous)
A (previous)
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Load Accumulator Sample (4 of 12)
MAR loaded with PC PC -gt MAR
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR (previous)
MAR 00110
MDR (previous)
A (previous)
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Load Accumulator Sample (5 of 12)
Memory Location 00110 Accessed and Contents
Placed in MDR
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR (previous)
MAR 00110
MDR (previous)
A (previous)
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Load Accumulator Sample (6 of 12)
Memory Location 00110 Accessed and Contents
Placed in MDR
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR (previous)
MAR 00110
MDR 01001111
A (previous)
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Load Accumulator Sample (7 of 12)
MDR copied to IR MDR -gt IR
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR 01001111
MAR 00110
MDR 01001111
A (previous)
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Load Accumulator Sample (8 of 12)
IR address part -gt MAR
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR 01001111
MAR 01111
MDR 01001111
A (previous)
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Load Accumulator Sample (9 of 12)
Location in MAR (01111) Accessed
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR 01001111
MAR 01111
MDR 01001111
A (previous)
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Load Accumulator Sample (10 of 12)
Contents of 01111 loaded into MDR
Memory
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR 01001111
MAR 01111
MDR 00001010
A (previous)
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Load Accumulator Sample (11 of 12)
Memory
IR op code executed MDR -gt A
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR 01001111
MAR 01111
MDR 00001010
A 00001010
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Load Accumulator Sample (12 of 12)
Memory
Finished !
Location 31 15 00001010 06
01001111 Location 0
PC 00110
IR 01001111
MAR 01111
MDR 00001010
A 00001010
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Load Fetch/Execute Cycle
PC -gt MAR Transfer the address from the PC to the MAR
MDR -gt IR Transfer the instruction to the IR
IR(address) -gt MAR Address portion of the instruction loaded in MAR
MDR -gt A Actual data copied into the accumulator
PC 1 -gt PC Program Counter incremented
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Store Fetch/Execute Cycle (1 of 2)
PC -gt MAR Transfer the address from the PC to the MAR
MDR -gt IR Transfer the instruction to the IR
IR(address) -gt MAR Address portion of the instruction loaded in MAR
A -gt MDR Accumulator copies data into MDR
PC 1 -gt PC Program Counter incremented
Notice how Step 4 differs for LOAD and STORE Notice how Step 4 differs for LOAD and STORE
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Store Fetch/Execute Cycle (2 of 2)
PC ? MAR MDR ? IR IRaddress ? MAR A ? MDR PC
1 ? PC
Fetch
time
Execute
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ADD Fetch/Execute Cycle (1 of 2)
PC -gt MAR Transfer the address from the PC to the MAR
MDR -gt IR Transfer the instruction to the IR
IR(address) -gt MAR Address portion of the instruction loaded in MAR
A MDR -gt A Contents of MDR added to contents of accumulator
PC 1 -gt PC Program Counter incremented
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ADD Fetch/Execute Cycle (2 of 2)
PC ? MAR MDR ? IR IRaddress ? MAR A MDR ?
A PC 1 ? PC
Fetch
time
Execute
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Add Instruction Sample (1 of 10)
New Task Value in location 7 is
10110010. Add instruction is 101. Value in
location 18 is seventy-one (i.e. binary
01000111) Everything else is as we left it!
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Add Instruction Sample (2 of 10)
PC PC 1
Memory
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 01001111
MAR 01111
MDR 00001010
A 00001010
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Add Instruction Sample (3 of 10)
Memory
PC -gt MAR
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 01001111
MAR 00111
MDR 00001010
A 00001010
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Add Instruction Sample (4 of 10)
Memory
MAR Accesses Location 00111
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 01001111
MAR 00111
MDR 00001010
A 00001010
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Add Instruction Sample (5 of 10)
Memory
Contents of 00111 -gt MDR
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 01001111
MAR 00111
MDR 10110010
A 00001010
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Add Instruction Sample (6 of 10)
Memory
MDR -gt IR
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 10110010
MAR 00111
MDR 10110010
A 00001010
60
Add Instruction Sample (7 of 10)
Memory
IR address -gt MAR
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 10110010
MAR 10010
MDR 10110010
A 00001010
61
Add Instruction Sample (8 of 10)
Memory
Location 10010 MAR Accessed
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 10110010
MAR 10010
MDR 10110010
A 00001010
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Add Instruction Sample (9 of 10)
Memory
Contents of 10010 -gt MDR
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 10110010
MAR 10010
MDR 01000111
A 00001010
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Add Instruction Sample (10 of 10)
IR opcode executed A A MDR
Memory
Location 31 18 01000111 15 00001010 07
10110010 06 01001111 Location 0
PC 00111
IR 10110010
MAR 10010
MDR 01000111
A 01010001
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Computer Buses
PCI Express BUS Card Slots (from top to bottom
x4, x16, x1, x16) compared to a traditional
32-bit PCI bus card slot.
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Buses (1 of 3)

• Group of electrical conductors (wires) for
  carrying signals from one location to another
• Line each conductor (or wire) in the bus
• The physical connection that makes it possible to
  transfer data from one location in the computer
  system to another
• 4 kinds of signals
• Data (alphanumeric, numerical, instructions)
• Addresses
• Control signals
• Power (sometimes)

66
Buses (2 of 3)
bus
Ports
Printer Mouse Keyboard Modem
Diskcontroller
Graphicscard
Monitor Speakers
CPU
Soundcard
RAM
Networkcard
Computer
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Buses (3 of 3)

• Connect CPU and Memory
• I/O peripherals on same bus as CPU/memory or
  separate bus
• If connect CPU, Memory and I/O modules in the
  same Physical package, called backplane
• Also called system bus or external bus
• Example of broadcast bus
• Common method of connecting CPU, Memory and I/O
  modules to a printed circuit board called
  motherboard

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Motherboard
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Types of Buses (1 of 2)

• Point-to-point
• When connect plug-in devices, called ports

Serial port
Modem
Control unit
ALU
70
Types of Buses (2 of 2)

• Multipoint to connect several points together

Computer
Computer
Computer
Computer
CPU
Memory
Disk controller
Video controller
71
Point-to-point vs. Multipoint
72
Bus Interface

• Bus interface bridges provide communication
  between different buses
• Special buses provide interconnections within the
  CPU chip
• Buses that form the backplane
• External CPU bus
• Peripheral control interface (PCI) bus
• Accelerated graphic processor (AGP)
• Industrial standard architecture (ISA)

73
Typical bus and port connections
Bus interface bridges connect different bus types
74
Bus Characteristics

• Protocol
• Documented agreement for communication
• Specification that spells out the meaning of each
  line and each signal on each line
• Throughput, i.e., data transfer rate in bits per
  second
• Data width in bits carried simultaneously
• Distance between two end points
• Type of signals unique/specialized or shared
• Addressing capacity
• Etc.

75
Buses Inside a Computer
CPU
Data bus Address bus Control bus
Memory
I/O Module
I/O Device
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Data Bus

• Carries data between the CPU and memory or I/O
  devices
• Bi-directional
• Data transferred out of the CPU for write
  operations
• Data transferred into the CPU for read
  operations
• Typical sizes 8, 16, 32, 64 lines
• Signal names
• D0, D1, D2, D3, etc.

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Address Bus

• Carries an address from the CPU to Memory or I/O
  devices
• Unidirectional
• The address is always supplied by the CPU
• (There is one exception to this, which well
  discuss later.)
• Typical sizes 16, 20, 24 lines
• Signal names
• A0, A1, A2, A3, etc.

78
Control Bus

• Collection of signals for coordinating CPU
  activities
• Each signal has a unique purpose
• Typical sizes 10-20 lines
• Signals are output, input, or bi-directional
• Typical signals
• /RD (read)
• /WR (write
• CLK (clock)
• /IRQ (interrupt request)
• etc.

79
PCI Bus Connections
80
PCI Bus

• 32- or 64-bit backplane
• Interconnects
• CPU
• Plug-in I/O (serial and parallel ports, sound
  cards, disc drives
• Lines are non-specialized carry addresses and
  data, labeled AD00 to AD31 (or AD63)
• Additional lines control and power lines

81
Instructions

• Instruction
• Direction given to a computer
• Causes electrical signals to be sent through
  specific circuits for processing
• Instruction set
• Design defines functions performed by the
  processor
• Differentiates computer architecture by the
• Number of instructions
• Complexity of operations performed by individual
  instructions
• Data types supported
• Format (layout, fixed vs. variable length)
• Use of registers
• Addressing (size, modes)

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Instruction Elements

• OPCODE task
• Source OPERAND(s)
• Result OPERAND
• Location of data (register, memory)
• Explicit included in instruction
• Implicit default assumed

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Instruction Format

• Machine-specific template that specifies
• Length of the op code
• Number of operands
• Length of operands

28 256 different instructions
Simple 32-bit Instruction Format
224 16 million memory addresses
84
Instruction Format IBM Mainframe
85
Instruction Types (1 of 2)

• Data Transfer (load, store)
• Most common, greatest flexibility
• Involve memory and registers
• Whats a word ? 16? 32? 64 bits?
• Arithmetic
• Operators - /
• Integers and floating point
• Logical or Boolean
• Relational operators gt lt
• Boolean operators AND, OR, XOR, NOR, and NOT
• Single operand manipulation instructions
• Negating, decrementing, incrementing

86
Instruction Types (2 of 2)

• Privileged
• Security
• Access control
• Not available to the application programs
• Bit manipulation instructions
• Flags to test for conditions
• Shift and rotate
• Program control
• Stack instructions
• Multiple data instructions
• I/O and machine control

87
Register Shifts and Rotates
88
Program Control Instructions

• Program control
• Jump and branch
• Subroutine call and return

89
Stack Instructions

• Stack instructions
• LIFO method for organizing information
• Items removed in the reverse order from that in
  which they are added

Push
Pop
90
Fixed Location Subroutine Return Address Storage
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Stack Subroutine Return Address Storage
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Multiple Data Instructions

• Perform a single operation on multiple pieces of
  data simultaneously
• SIMD Single Instruction, Multiple Data
• Intel MMX? 57 multimedia instructions
• Commonly used in vector and array processing
  applications

93
Thank you!
Reading Lecture slides and notes, Chapter 7
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