Single Cycle CPU

1
Single Cycle CPU

• Questions on CS140 ?
• Computer Arithmetic ?
• Attend office hours with TAs or me.
• Do the exercises in the text.

• Previously built and ALU.
• Today Actually build a CPU

2
The Story so far

• Instruction Set Architectures
• Performance issues
• 2s complement, Addition, Subtraction
• Multiplication, Division, Floating Point numbers

Basically ISA ALU stuff
3
CPU Building blocks
CarryIn

• Adder
• MUX

A
32
Sum
Adder
32
B
Carry
32
Select
A
32
MUX
Y
32
B
32
OP
A
32
Result
ALU
32
B
32
4
CPU Building blocks

• Building a 64-bit adder from 2x32-bit adders

5
CPU Building blocks

• Silicon is cheap sort-of

6
CPU
Single Cycle CPU
7
CPU
The Big Picture Where are We Now?

• The Five Classic Components of a Computer
• Datapath Design, then Control Design

Processor
Input
Memory
Output
8
CPU The big picture
Execute
Decode
Fetch
Fetch
Store
Next
Execute an entire instruction
Design hardware for each of these steps!!!
9
CPU Clocking
Clk
Setup
Hold
Setup
Hold
Dont Care

• All storage elements are clocked by the same
  clock edge

10
CPU
The Big Picture The Performance Perspective

• Execution Time Insts CPI Cycle Time
• Processor design (datapath and control) will
  determine
• Clock cycle time
• Clock cycles per instruction
• Starting today
• Single cycle processor
• Advantage One clock cycle per instruction
• Disadvantage long cycle time

Execute an entire instruction
11
CPU

• We're ready to look at an implementation of the
  MIPS
• Simplified to contain only
• memory-reference instructions lw, sw
• arithmetic-logical instructions add, sub, and,
  or, slt
• control flow instructions beq
• Generic Implementation
• use the program counter (PC) to supply
  instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do
• All instructions use the ALU after reading the
  registers memory-reference? arithmetic? control
  flow?

12
CPU
Review The MIPS Instruction Formats

• The different fields are
• op operation of the instruction
• rs, rt, rd the source and destination register
  specifiers
• shamt shift amount
• funct selects the variant of the operation in
  the op field
• address / immediate address offset or immediate
  value
• target address target address of the jump
  instruction

13
CPU

• R-type
• add rd, rs, rt
• sub, and, or, slt
• LOAD and STORE
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH
• beq rs, rt, imm16

14
CPU
Requirements to implement the ISA

• Memory
• instruction data
• Registers (32 x 32)
• read RS
• read RT
• Write RT or RD
• PC
• Extender
• Add and Sub register or extended immediate
• Add 4 or extended immediate to PC

15
CPU

• Combinational Elements
• Storage Elements
• Clocking methodology

A
State Element
C f(A,B,state) Staten f(A,B,staten-1)
B
clk
A
Combinational Logic
C f(A,B)
B
16
CPU Storage unit

• The set-reset latch
• output depends on present inputs and also on past
  inputs

17
CPU D-flip flop

• Two inputs
• the data value to be stored (D)
• the clock signal (C) indicating when to read
  store D
• Two outputs
• the value of the internal state (Q) and it's
  complement

• Output changes only on the clock edge

18
CPU Clocking Methodology

• An edge triggered methodology
• Typical execution
• read contents of some state elements,
• send values through some combinational logic
• write results to one or more state elements

19
CPU Storage block
Write Enable

• Register
• Similar to the D Flip Flop except
• N-bit input and output
• Write Enable input
• Write Enable
• 0 Data Out will not change
• 1 Data Out will become Data In (on the clock
  edge)

Data In
Data Out
N
N
Clk
20
CPU Register Files
RW
RA
RB
Write Enable
5
5
5

• Register File consists of (32) registers
• Two 32-bit output buses
• One 32-bit input bus busW
• Register is selected by
• RA selects the register to put on busA
• RB selects the register to put on busB
• RW selects the register to be writtenvia busW
  when Write Enable is 1
• Clock input (CLK)
• Factor only during write-enable1
• Otherwise, this unit acts just like combinational
  logic.

busA
busW
32
32 32-bit Registers
32
busB
Clk
32
21
CPU Register Files
Still use the real clock (not shown here) to do
the actual write
Built using D-flip flops
22
CPU Memory
Write Enable
Address

• Memory (idealized)
• One input bus Data In
• One output bus Data Out
• Memory word is selected by
• Address selects the word to put on Data Out
• Write Enable 1 address selects the memoryword
  to be written via the Data In bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a
  combinational logic block
• Address valid gt Data Out valid after access
  time.

Data In
DataOut
32
32
Clk
23
CPU RTL
Register Transfer Language (RTL)

• is a mechanism for describing the movement and
  manipulation of data between storage elements
• R3 lt- R5 R7
• PC lt- PC 4 R5
• Rrd lt- Rrs Rrt
• Rrt lt- MemRrs immed

24
CPU More building blocks
25
CPU The big picture
Execute
Decode
Fetch
Fetch
Store
Next
Execute an entire instruction
Design hardware for each of these steps!!!
26
CPU Instruction Fetch

• RTL version of the instruction fetch step
• Fetch the Instruction memPC
• Update the program counter
• Sequential Code PC lt- PC 4
• Branch and Jump PC lt- something else

Instruction Word
32
27
CPU Binary arithmetic for PC

• In theory, the PC is a 32-bit byte address into
  the instruction memory
• Sequential operation PClt310gt PClt310gt 4
• Branch operation PClt310gt PClt310gt 4
  SignExtImm16 4
• The magic number 4 always comes up because
• The 32-bit PC is a byte address
• And all our instructions are 4 bytes (32 bits)
  long
• In other words
• The 2 LSBs of the 32-bit PC are always zeros
• There is no reason to have hardware to keep the 2
  LSBs
• In practice, we can simplify the hardware by
  using a 30-bit PClt312gt
• Sequential operation PClt312gt PClt312gt 1
• Branch operation PClt312gt PClt312gt 1
  SignExtImm16
• In either case Instruction Memory Address
  PClt312gt concat 00

28
CPU Instruction Fetch unit

• The common RTL operations
• Fetch the Instruction inst lt- memPC
• Update the program counter
• Sequential Code PC lt- PC 4
• Branch and Jump PC lt- something else

29
CPU Register-Register Operations (Add, Subtract
etc.)

• Rrd lt- Rrs op Rrt Example addU rd,
  rs, rt
• Ra, Rb, and Rw come from instructions rs, rt,
  and rd fields
• ALUctr and RegWr control logic after decoding
  the instruction

Rs
Rt
Rd
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
busB
Clk
32
Worry about instruction decode to generate
ALUctr and RegWr later.
30
CPU Register - Register Timing
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
RegWr
Old Value
New Value
Register File Access Time
busA, B
Old Value
New Value
ALU Delay
busW
Old Value
New Value
Rs
Rt
Rd
ALUctr
Register Write Occurs Here
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
31
CPU Logical Immediate Op.

• Rrt lt- Rrs op ZeroExtimm16

Handle Rt as destination
Rt
Rd
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
Result
32
32 32-bit Registers
ALU
32
32
Clk
busB
32
Mux
Handle Immediate as operand
ZeroExt
imm16
32
16
ALUSrc
32
CPU Load Operations

• Rrt lt- MemRrs SignExtimm16 Example lw
  rt, rs, imm16

Rt
Rd
Reg-Write could be from result or data memory
Need data Memory!
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
busA
W_Src
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
MemWr
32
Mux
Mux
WrEn
Adr
Data In
32
Data Memory
32
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
33
CPU Store Operations

• Mem Rrs SignExtimm16 lt- Rrt Example
  sw rt, rs, imm16

Reg can write to Data Memory
Rt
Rd
ALUctr
MemWr
W_Src
RegDst
Mux
Rs
Rt
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
32
Mux
Mux
WrEn
Adr
Data In
32
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
34
CPU Branching

• beq rs, rt, imm16
• memPC Fetch the instruction from memory
• Equal lt- Rrs Rrt Calculate the branch
  condition
• if (COND eq 0) Calculate the next instructions
  address
• PC lt- PC 4 ( SignExt(imm16) x 4 )
• else
• PC lt- PC 4

35
CPU Datapath for Branching

• beq rs, rt, imm16 Datapath generates
  condition (equal)

Inst Address
nPC_sel
32
00
imm16
Calculate the condition part of the branch op.
PC Ext
Calculate (PC4) as well as (imm16PC4) and
choose one
36
CPU The Aggregate Datapath
Instructionlt310gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Still need to worry about Instruction Decode
Imm16
Rd
Rt
Rs
RegDst
ALUctr
MemtoReg
MemWr
nPC_sel
Equal
Rt
Rd
0
1
Rs
Rt
4
RegWr
5
5
5
busA
Rw
Ra
Rb

busW
00
32
32 32-bit Registers
ALU
0
32
busB
32
0
PC
32
Mux
Mux
Clk
32
WrEn
Adr
1
Clk
1
Data In
Extender
Data Memory
imm16
PC Ext
32
16
imm16
Clk
ExtOp
ALUSrc
37
CPU Datapath High-level view

• Register file and ideal memory
• The CLK input is a factor ONLY during write
  operation
• During read operation, behave as combinational
  logic
• Address valid gt Output valid after access time.

Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Instruction Address
A
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
38
CPU Control Signals
Instructionlt310gt
Inst Memory
lt2125gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
MemtoReg
MemWr
nPC_sel
ALUSrc
RegDst
ExtOp
RegWr
Equal
DATA PATH
39
CPU Control Signals Meaning

• Rs, Rt, Rd and Imed16 hardwired into datapath
• nPC_sel 0 gt PC lt PC 4 1 gt PC lt PC 4
  SignExt(Im16) 00

nPC_sel
4
00
PC
Clk
imm16
PC Ext
40
CPU Control Signals Meaning

• ExtOp zero, sign
• ALUsrc 0 gt regB 1 gt immed
• ALUctr add, sub, or

• MemWr write memory
• MemtoReg 1 gt Mem
• RegDst 0 gt rt 1 gt rd
• RegWr write dest register

RegDst
ALUctr
MemtoReg
MemWr
Equal
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
0
32
busB
32
0
32
Mux
Mux
Clk
32
WrEn
Adr
1
1
Data In
Data Memory
imm16
Extender
32
16
Clk
ExtOp
ALUSrc
41
CPU Control Signals for various operations
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc RegB, ALUctr sub, RegDst rd,
RegWr, nPC_sel 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Z, ALUctr or, RegDst rt, RegWr,
nPC_sel 4 LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Sn, ALUctr add, MemtoReg,
RegDst rt, RegWr, nPC_sel 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrs PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add, MemWr,
nPC_sel 4 BEQ if ( Rrs Rrt ) then PC
lt PC sign_ext(Imm16) 00 else PC lt PC
4 nPC_sel EQUAL, ALUctr sub
42
CPU Control Signals Logic Design

• nPC_sel lt if (OP BEQ) then EQUAL else 0
• ALUsrc lt if (OP 000000) then regB else
  immed
• ALUctr lt if (OP 000000) then
  funct elseif (OP ORi) then OR elseif
  (OP BEQ) then sub else add
• ExtOp lt _____________
• MemWr lt _____________
• MemtoReg lt _____________
• RegWr lt_____________
• RegDst lt _____________

43
CPU Control Signals Logic Design

• nPC_sel lt if (OP BEQ) then EQUAL else 0
• ALUsrc lt if (OP 000000) then regB else
  immed
• ALUctr lt if (OP 000000) then
  funct elseif (OP ORi) then OR
  elseif (OP BEQ) then sub else
  add
• ExtOp lt if (OP ORi) then zero else sign
• MemWr lt (OP Store)
• MemtoReg lt (OP Load)
• RegWr lt if ((OP Store) (OP BEQ)) then
  0 else 1
• RegDst lt if ((OP Load) (OP ORi)) then
  0 else 1

44
CPU Example Load
Rrt lt- MemRrs SignExtimm16 Viz., lw
rt, rs, imm16
45
CPU The abstract version
Control
Ideal Instruction Memory
Control Signals
Conditions
Instruction
Rd
Rs
Rt
5
5
5
Instruction Address
A
Data Address
Data Out
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
Datapath

• Logical vs. Physical Structure

46
CPU The real thing
47
CPU 5 steps to design

• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• MIPS makes it easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
• Single cycle datapath gt CPI1, CCT gt long

48
CPU Control Section

• The Five Classic Components of a Computer

49
CPU Add Instruction

• add rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt- Rrs Rrt The actual operation
• PC lt- PC 4 Calculate the next
  instructions address

50
CPU The Add Instruction

• Fetch the instruction from Instruction memory
  Instruction lt- memPC
• This is the same for all instructions

Instruction Fetch Unit at the Beginning of Add
PC Ext
51
CPU The Add Instruction
The Single Cycle Datapath during Add

• Rrd lt- Rrs Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 1
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 0
busA
MemWr 0
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
52
CPU The Add Instruction

• PC lt- PC 4
• This is the same for all instructions except
  Branch and Jump

Instructionlt310gt
nPC_sel
4
Instruction Fetch Unit at the End of Add
00
PC
Clk
imm16
53
CPU The Or Immediate Instruction

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
MemWr
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
54
CPU The Or Immediate Instruction
The Single Cycle Datapath during Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Or
RegWr 1
MemtoReg 0
5
5
5
busA
MemWr 0
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 0
55
CPU The Load Instruction
The Single Cycle Datapath during Load

• Rrt lt- Data Memory Rrs SignExtimm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
MemtoReg 1
5
5
5
busA
MemWr 0
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
56
CPU The Store Instruction
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
MemWr
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
57
CPU The Store Instruction
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
MemWr 1
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
58
CPU Datapath during branch

• if (Rrs - Rrt 0) then Zero lt- 1
  else Zero lt- 0

Instructionlt310gt
nPC_sel Br
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Subtract
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
MemtoReg x
5
5
5
busA
MemWr 0
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
59
CPU Datapath during branch

• if (Zero 1) then PC PC 4
  SignExtimm164 else PC PC 4

Instructionlt310gt
nPC_sel
Instruction Fetch Unit at the End of Branch
4
00
PC
Clk
imm16
60
CPU Creating control from Datapath
Inst Memory
lt2125gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
MemtoReg
MemWr
nPC_sel
ALUSrc
RegDst
ExtOp
RegWr
Equal
DATA PATH
61
CPU Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc RegB, ALUctr sub, RegDst rd,
RegWr, nPC_sel 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Z, ALUctr or, RegDst rt, RegWr,
nPC_sel 4 LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Sn, ALUctr add, MemtoReg,
RegDst rt, RegWr, nPC_sel 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrs PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add, MemWr,
nPC_sel 4 BEQ if ( Rrs Rrt ) then PC
lt PC sign_ext(Imm16) 00 else PC lt PC
4 nPC_sel Br, ALUctr sub
62
CPU Summary of Control Signals
func
10 0000
See
10 0010
We Dont Care -)
Appendix A
op
00 0000
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
add, sub
I-type
ori, lw, sw, beq
J-type
jump
63
CPU Summary of Control Signals
The Concept of Local Decoding
func
ALUctr
op
6
Main Control
3
ALUop
6
N
ALU
64
CPU Encoding of ALUop

• In this exercise, ALUop has to be 2 bits wide to
  represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, and (4) Subtract
• To implement the full MIPS ISA, ALUop has to be 3
  bits to represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, (4) Subtract, and (5) And
  (Example andi)

R-type
ori
lw
sw
beq
jump
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUoplt20gt
1 00
0 10
0 00
0 00
xxx
0 01
65
CPU Decoding of the func field
Recall
66
CPU Truth table for ALUctr
functlt30gt
Instruction Op.
0000
add
0010
subtract
0100
and
0101
or
1010
set-on-less-than
67
CPU Logic Equation ALUctr2
The Logic Equation for ALUctrlt2gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt2gt
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
This makes funclt3gt a dont care

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt

68
CPU Logic Equation ALUctr1
The Logic Equation for ALUctrlt1gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt1gt
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

• ALUctrlt1gt !ALUoplt2gt !ALUoplt0gt
• ALUoplt2gt !funclt2gt !funclt0gt

69
CPU Logic Equation ALUctr0
The Logic Equation for ALUctrlt0gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt0gt
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1

• ALUctrlt0gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

70
CPU ALU Control block
The ALU Control Block

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt
• ALUctrlt1gt !ALUoplt2gt !ALUoplt0gt
• ALUoplt2gt !funclt2gt !funclt0gt
• ALUctrlt0gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

71
CPU Main Control
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegDst
1
0
0
x
x
x
ALUSrc
0
1
1
1
0
x
MemtoReg
0
0
1
x
x
x
RegWrite
1
1
1
0
0
0
MemWrite
0
0
0
1
0
0
Branch
0
0
0
0
1
0
Jump
0
0
0
0
0
1
ExtOp
x
0
1
1
x
x
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUop lt2gt
1
0
0
0
x
0
ALUop lt1gt
0
1
0
0
x
0
ALUop lt0gt
0
0
0
0
x
1
72
CPU Main Control
The Truth Table for RegWrite
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegWrite
1
1
1
0
0
0

• RegWrite R-type ori lw
• !oplt5gt !oplt4gt !oplt3gt !oplt2gt !oplt1gt
  !oplt0gt (R-type)
• !oplt5gt !oplt4gt oplt3gt oplt2gt !oplt1gt
  oplt0gt (ori)
• oplt5gt !oplt4gt !oplt3gt !oplt2gt oplt1gt
  oplt0gt (lw)

RegWrite
73
CPU Main Control
PLA Implementation of the Main Control
RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUoplt2gt
ALUoplt1gt
ALUoplt0gt
74
CPU
Putting it All Together A Single Cycle Processor
ALUop
ALU Control
ALUctr
3
func
RegDst
op
3
Main Control
Instrlt50gt
6
ALUSrc
6

Instrlt3126gt
Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
MemWr
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Instrlt150gt
Clk
ALUSrc
ExtOp
75
CPU
Worst Case Timing (Load)
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memoey Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
ExtOp
Old Value
New Value
ALUSrc
Old Value
New Value
MemtoReg
Old Value
New Value
Register Write Occurs
RegWr
Old Value
New Value
Register File Access Time
busA
Old Value
New Value
Delay through Extender Mux
busB
Old Value
New Value
ALU Delay
Address
Old Value
New Value
Data Memory Access Time
busW
Old Value
New
76
CPU Single Cycle Solution

• Long cycle time
• Cycle time must be long enough for the load
  instruction
• PCs Clock -to-Q
• Instruction Memory Access Time
• Register File Access Time
• ALU Delay (address calculation)
• Data Memory Access Time
• Register File Setup Time
• Clock Skew
• Cycle time for load is much longer than needed
  for all other instructions

77
CPU Single Cycle Solution

• Single cycle datapath gt CPI1, CCT gt long
• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• Control is the hard part
• MIPS makes control easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates

78
CPU Interrupts

• Datapath for interrupts
• Interrupt basically hardware line requesting an
  immediate jump
• PC IntI if IntI 1
• May or maynot save registers
• May or maynot be maskable.
• Useful for multitasking control real-time
  processing
• Signal Processing
• Harder to implement in case of a
  multi-cycle/pipelines system !