FFT Components: Signed 2

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FFT ComponentsSigned 2s Compliment Complex
Multiplier

• FDR December 12, 2005
• Shin Horiuchi
• David Schwarzenberg (leader)

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Outline

• Project definition
• Pin assignments
• Ripple Carry Adder/Subtractor
• Multiplier
• FIFO
• Simulation Procedures and Results
• Layouts and Final Numbers
• 100MHz goal
• What still must be done
• Bar chart of schedule of tasks

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Project Description

• Signed 2s compliment complex multiplier. This
  multiplier must be able to operate at speeds of
  100MHz or faster. The output should have
  separate real and imaginary answers. The complex
  multiplier will be used in a FFT. This FFT will
  also require the use of the same complex adder
  and subtractor used to construct the multiplier.

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Project Objectives

• Obtain further knowledge of CMOS VLSI design. To
  gain experience working in teams, and with other
  teams. To document the design process in a
  professional manner, producing a final, public
  document.

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Gajski Diagram
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40 Pins

• The VLSI chip is limited to 40 pins, and the
  input and output must be done in parallel with
  signed binary numbers

Outputs The product of two 3-bit signed numbers
is an 6-bit number and a sign bit. The
sum/difference of two 6-bit numbers is 7-bits
plus a sign bit for a total of 8-bits. Total
outputs 16 pins
Inputs a, b, c, d Each can be 3-bits with a sign
bit. This will take 4 pins each Total inputs
16-pins
Reserved 2 Ground Pins 2 Vdd Pins
Total 16168 40 pins
2 Clock Pins 2 Reset Pins
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Pin Assignments
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Simulating the Circuits

• It is important to test each sub circuit for
  correct operation and performance before it is
  added into the system
• The testing method used involves determining the
  most relevant test cases.
• Pulsed waveforms must be used to discover circuit
  delays.

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Basic Requirements
This operation requires Four 4x4-bit
Multipliers ac, bd, bc, ad One 88-bit Adder
bcad One 8-8-bit Subtraction ac-bd (Must
Accept Signed 2s Compliment)
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Full and Half Adder
Comprises the larger adders and the multiplier
needed.

• The full adder has two inputs and a carry in.
  This has a sum and carry out.
• The carry and sum both must propagate across two
  gates, this has two gate delay times.

• The half adder does not have a carry in. This
  reduces functionality, but with less gates, it
  can save space and time when a carry in is not
  needed.

The Full and Half Adders used are from the ADK
library. These consume less power (31), take
less layout space, make the layout more coherent
and have smaller delays.
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Full Adder Simulation

• A pulsed waveform with periods 4, 8 and 16ns was
  used to simulate all different input combinations
• The full adder used is from ADK library so it
  should work, but gathering delay information is
  important.

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Full Adder Simulations
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Ripple Carry Adder

• Beat out the carry look ahead because of
  simplicity and operates fast enough
• Maximum simulated delay of 5ns
• Handles signed 2s compliment

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Ripple Carry Adder
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Ripple Carry Adder Simulations

• The maximum delay occurs when there is the
  maximum number of carries

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Ripple Carry Adder Simulations
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Ripple Carry Subtractor

• 2s compliment is accomplished by inverting the
  second input and adding a carry.
• This also can handle numbers that are already
  signed 2s compliment

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Ripple Carry Subtractor
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Ripple Carry Subtractor Simulations

• If the circuit is pushed from all high, to all
  low there will be a borrow across every full
  adder
• This will cause the maximum possible delay

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Ripple Carry Subtractor Simulations
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4x4 Multiplier

• Can find the product of two signed 2s compliment
  numbers
• Uses the add and shift method to calculate the
  product

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4x4 Multiplier
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Multiplier Simulation

• Care needs to be taken to make sure the correct
  number and sign is calculated using the
  multiplier. If there is a bad link, it will
  corrupt further answers. This makes it easy to
  isolate errors.
• Positive-positive negative-positive and
  negative-negative situations must be tested.

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Multiplier Simulations-3x-618
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Multiplier Simulations-1x1-1
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Un-Clocked System
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Final System SimulationsUn-clocked Case 1
Imaginary Outputs
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Final System SimulationsUn-clocked Case 1 Real
Outputs
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Timing FIFO

• Will sample and hold on the rising edge.
• Sample and hold the input as well as the output.
• ADK DFFR is used, a D flip-flop with reset.
• Reset is needed so that the status of the FIFO is
  known.

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Final Schematic
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Timing Diagram
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Final System Simulations

• Test the system for various test cases
• A simulation of the whole system would be time
  consuming and difficult to gather good results.
• Test un-clocked first to see the delays
• Then test the clocked, with an appropriate clock
  to see if it works fast enough

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Final System SimulationsUn-clocked Case
Imaginary Outputs
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Final System SimulationsClocked Case Imaginary
Outputs
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Final System SimulationsUn-clocked Case Real
Outputs
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Final System SimulationsClocked Case Real
Outputs
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Layouts Automatic Layout
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Final Layout

• 2048 x 2056 lambda, 1.024mm x 1.028mm
• Simulated power consumption of 35nW

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Layouts Final
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100MHz

• The goal is to achieve a circuit that operates
  with a 100MHz clock.
• The simulations show the final circuit can be
  sampled after 7.5ns. If a clock is used with a
  duty cycle of 75 at 100MHz, the output FIFO will
  sample after 7.5ns.
• If a clock with a duty cycle of 50 is used, the
  circuit can only be expected to run at 67MHz.

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What needs to be done

• Send out completed layout to be fabricated
• Receive chip back
• Test chip
• Final report with testing results

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Bar Chart Schedule of Tasks(10/25/2005)
    September September September September October October October October October November November November November December December
Tasks   1 8 15 22 1 8 15 22 29 5 12 19 26 3 10
Research   X X X                        
Decision Making       X X X X X X              
Design Circuits (modules)             X X X              
Enter sub-modules                 X X            
Simulate sub-modules                 X X X          
Develop sub-systems                     X X        
Simulate sub-systems                     X X X X    
Integrate sub-systems                     X X X X    
Simulate Integrated sub-systems                         X X X  
Write Report                     X X X X X X
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Bar Chart Schedule of Tasks(11/17/2005)
    September September September September October October October October October November November November November December December
Tasks   1 8 15 22 1 8 15 22 29 5 12 19 26 3 10
Research   X X X                        
Decision Making       X X X X X X              
Design Circuits (modules)             X X X              
Enter sub-modules                 X X            
Simulate sub-modules                 X X X          
Develop sub-systems                     X X        
Simulate sub-systems                     X X X X    
Integrate sub-systems                     X X X X    
Simulate Integrated sub-systems                         X X X  
Write Report                     X X X X X X
Dates Missed in Yellow
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Bar Chart Schedule of Tasks(12/12/2005)
    September September September September October October October October October November November November November December December
Tasks   1 8 15 22 1 8 15 22 29 5 12 19 26 3 10
Research   X X X                        
Decision Making       X X X X X X              
Design Circuits (modules)             X X X              
Enter sub-modules                 X X            
Simulate sub-modules                 X X X          
Develop sub-systems                     X X        
Simulate sub-systems                     X X X    
Integrate sub-systems                     X X    
Simulate Integrated sub-systems                         X X X  
Write Report                     X X X X X
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References

• http//www.asic-world.com/digital/index.html
• http//www.seas.upeen.edu/ese201/lab/CarryLookAhe
  ad/CarryLookAheadF01.html
• http//tima-cmp.imag.fr/guyot/Cours/Oparithm/engl
  ish/Multip.htm
• http//www.play-hookey.com/digital/

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Thank You

• Dr. Andrzej Rucinski
• Frank Hludik 
• Tomasz Jankowski
• Jakub Mocny
• Classmates