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ASIC FFT Library: 8-bit Complex Multiplier

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Title: ASIC FFT Library: 8-bit Complex Multiplier


1
ASIC FFT Library8-bit Complex Multiplier
  • Final Design Review 12/12/2005
  • Team Kevin Arruda (Lead) Jordan Wyckoff
  • Course ECE 715

2
Outline
  • Goals Specifications
  • Design Process
  • Simulation Design Verification
  • Achieved Specification
  • Project Timeline
  • Whats Next

3
Goals Specifications
  • Project definition The goal of this project is
    to design, simulate, and implement a functional
    complex multiplier to be used in creating a
    16-point radix-4 FFT algorithm.
  • ASIC using .5um technology.
  • 100 MHz clock speed
  • Must accommodate 2s compliment integer operands
    which form an 8 bit complex number.
  • Synchronous input/output.
  • Of Other Concern
  • Working Chip
  • Efficient Design
  • Gain insight into real-world VLSI design

4
Design Process
  • Research
  • Multiplier/Adder Designs (j,k)
  • 2s Compliment Mathematics (j,k)
  • Physical Layout (k)
  • Implementation
  • Initial functional specification (j,k)
  • Initial schematic design and implementation (j)
  • Functionality based simulation and testing (j)
  • Layout design (k)
  • Determine performance capacity (j)
  • Documentation (k)

(j) Jordan (k) Kevin
5
Research
  • Complex Multiplication
  • a, b, c, d gt 4-bit 2s compliment int
  • (ajb)(cjd)
  • (ac adj bcj bd)
  • (ac bd) (ad bc)j P v

6
Research (cont.)
Initial Design for half adder and full adder
7
Research (cont.)
Initial Design for our Multiplier
  • Design Issues
  • Overflow issues
  • Integer range
  • Product is twice the size of inputs
  • 4bit input ? 8bit output
  • 2s compliment compatible?

8
Research (cont.)
  • 2s Compliment
  • Multiplier must accommodate 2s Compliment
    integers.
  • Simple binary multipliers do not. (Sign Bit)
  • Quick Review
  • Binary 111 4 2 1 7
  • 2s Compliment 111 -4 2 1 -1
  • The MSB always represents the sign. 0 for
    positive, 1 for negative.
  • This reduces the possible range of positive
    numbers in exchange
  • for the ability to represent negatives.

9
Research (cont.)
  • Optimized Multiplier
  • Includes Hierarchy of half adders and full
    adders
  • 2s Compliment compatible!
  • MSB is inverted, as well as several gates
  • Extra carry-in of 1 is included in addition
    process

10
Implementation
  • 8-bit Ripple Carry Adder

Cascaded half-adders and full-adders
Half Adder
Full Adder
11
Implementation
  • 8-bit Subtractor
  • Boolean Algebra
  • A B C A (-B)
  • (-B) B 0001 (2s compliment)
  • This component is similar to the 8 bit adder
  • Uses a hierarchy of full adders
  • All bits from input B are inverted
  • Extra value of 1 is added into sequence

12
Implementation
  • 2s Compliment Multiplier

Timing Characteristics
13
Implementation
  • 8-bit Complex Multiplier
  • Simple Combination of previous components
  • 18 output bits, 16 for numerical output, 2 for
    overflow detection
  • Schematic does not currently show input and
    output buffers

14
Simulation
  • First Simulation
  • All inputted bits set to 5 V
  • Check timing characteristics
  • Results
  • Basic functionality works
  • outputs are unstable
  • latches must be introduced at inputs and
    outputs to solve synchronization issues.

15
Simulation (cont.)
Maximum delay path 4 ns
16
Implementation II
  • DFF latches
  • 16-bit and 18-bit DFF latches appended at inputs
    and outputs.
  • Inputs are latched no rising edge of clock
  • Outputs are latched on falling edge of clock

17
Implementation II
18
Simulations (cont.)
  • INPUTS
  • (AjB)(CjD)Re jIm
  • A 0101 (5)
  • B 1011 (-5)
  • C 1110 (-2)
  • D 0110 (6)

19
Simulations (cont.)
  • OUTPUTS (real)
  • (AjB)(CjD)Re jIm
  • Re 00010100 (20)

20
Simulations (cont.)
  • OUTPUTS (imaginary)
  • (AjB)(CjD)Re jIm
  • Im 00101000 (40)

21
Simulation (cont.)
Verification
(AjB)(CjD)Re jIm From simulation inputs A
5 B -5 C -2 D 6 Expected outputs.
Re 20 Im 40
Outputs from simulation Re 00010100 20
Im 00101000 40 Complex Multiplier Works!!
22
Layout
  • 2,361 l X 2117 l
  • Mostly auto-routed core logic
  • Manually routed padframe
  • Uses all 40 pins available (16 in, 2 Vdd, 2 GND,
    1 CLK, 1 RESET, 18 out)

23
Design Results
  • Maximum clock speed
  • -Safe 100Mhz
  • Chip-area Usage
  • -W (2,361 l) x L (2,117 l) 4998237 sq. L (l
    .5um)
  • -W (1180.5 um) x L (1058.5 um) 1249559.25 sq.
    um
  • -W ( 1.1805 mm) x L (1.0585 mm) 1.24955925
    sq. mm
  • Power Dissapation
  • 35.6839nW / operation
  • Slew Rate of Output
  • -Risetime 49.011 Ps
  • -Falltime 37.250 Ps
  • Design Flaws and weaknesses?
  • -No CLA logic
  • -Small of bits (albeit maximum, need more for
    16-point FFT!)

24
Project plan
Agenda - project preparation - project
design - project simulation - report
25
Whats Next?
  • Testing of manufactured chip
  • Comparison to rival technologies (PLDs)
  • Hind-sight improvement ideas

26
References Acknowledgements
  • ECE715 Classmates
  • Frank Hludik
  • Dr. Andrzej Rucinski
  • Tomasz Jankowski, Jakub Mocny

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