INTERCONNECT MODELING M.Arvind 2nd M.E Microelectronics

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INTERCONNECT MODELINGM.Arvind2nd M.E
Microelectronics
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OVERVIEW

• Introduction to On-Chip interconnects
• Modeling the parasitics
• Elmore Delay Model
• Repeater insertion
• Min delay condition
• Power Model
• Optimizing Power

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Introduction to On-chip interconnects

• Wires linking the transistors together
• Three types of interconnects
• Local
• Semi-global and
• Global interconnect

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Introduction to On-chip interconnects

• Can be modeled as R, RC, LC, RLC or RLGC network.

Power lines R,RL
Signal lines C, RC
Clock lines buses RLC
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Modeling a piece of wire
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Capacitance Modeling

• Capacitance
• cw 2 (cg cf cc )
• cf is the coupling factor

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Capacitance Modeling (cont)

• cg has 2 components cg1, cg2

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Simplified Capacitance Model

• For a circuit designer
• ILDT, h and e are fixed. Therefore,

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Fringing Effects
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Modeling Wire Resistance

• Resistance

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Pros and Cons of Cu

• Pros
• Better electro-migration resistance
• Cons
• Cu atoms diffuses into SiO2
• Cladding layers of TiN, Si3N4 used to prevent
  this
• Increases the resistance

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Elmore Delay Model

• Delay of a RC network is given by

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Delay of a long wire

• Delay grows quadratic
• Hence need repeaters

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Repeater Insertion

• Repeaters are placed to reduce delay

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Repeater Insertion (cont)

• Delay grows linear

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Modeling the repeater

• Repeater is a large inverter (5-25µm) placed
  in-between interconnect lines.
• Cgate, Cp a size of the repeater
• RT VDD/2Iavg, where Iavg ?Iddt in the
  interval Td

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Modeling the repeater (cont)
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Delay equations

• Delay of an interconnect segment is
• Total delay is

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Optimal Repeater Size and Spacing

• The minimum delay condition

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Power modeling

• Total power dissipated in the interconnect
  network is given by
• Ptotal Pdy Psc Pleak
• Pdy ?Ctotal V²ddf
• Psc ?Isc per µm Vdd Wtotalftt
• Pleak Ileak per µm WtotalVdd
• Where ? is the switching factor, tt is the time
  taken for the input to transit from Vthn to
  Vdd Vthp

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Power modeling (cont)
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Optimizing power

• Min delay does not imply min power

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Techniques to Reduce Power

• Can be reduced by decreasing
• Supply voltage
• Size of repeaters
• Number of repeaters

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Optimal Power Delay Tradeoff
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References

• William J.Dally John W.Poulton., Digital Systems
  Engineering Cambridge University Press,1998
• Kaustav Banerjee et al., A power-optimal
  insertion methodology for global interconnects in
  nanometer designs IEEE TRANSACTION ON ELECTRON
  DEVICES, VOL. 49, NO. 11, NOVEMBER 2002
• Kaustav Banerjee et al., A global interconnect
  optimization scheme for nanometer scale VLSI with
  implications for latency, bandwidth, and power
  dissipation IEEE TRANSACTION ON ELECTRON
  DEVICES. VOL. 51, NO.2, FEBRUARY 2004.

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• Thank You