EGR 277

1
Lecture 9 EGR 262 Fundamental Circuits Lab
EGR 262 Fundamental Circuits Lab Presentation
for Lab 9 Digital-to-Analog Conversion -
Revisited
Instructor Paul Gordy Office H-115 Phone
822-7175 Email PGordy_at_tcc.edu
2
Lecture 9 EGR 262 Fundamental Circuits Lab

• Lab 5
• DAC built using an R-2R ladder network
• 3 outputs required to provide 3 bits of precision
  (23 8 analog output levels)
• Lab 9
• DAC built using a PWM signal to charge a
  capacitor to the desired analog level
• The average capacitor voltage is proportional to
  the duty cycle of the PWM output
• 1 output required to provide 6 bits of precision
  (26 64 analog output levels)

3
Lecture 9 EGR 262 Fundamental Circuits Lab
RC Circuits Recall from EGR 260 the responses for
charging and discharging capacitor
voltages. Charging capacitor
v(t)
Vx
t
0
5? 5RC
0
Discharging capacitor
v(t)
Vx
t
0
5? 5RC
0
4
Lecture 9 EGR 262 Fundamental Circuits Lab
Time to charge or discharge a capacitor The time
to charge or discharge a circuit is often
expressed in terms of ? (tau), the time
constant for the circuit. For an RC circuit, ?
RC. The time to charge a capacitor to about
95 of its final value is about 3? 3RC since
v(3? ) Vx(1-e-t/RC) Vx(1-e-3RC/RC) Vx(1-e-3)
0.95Vx. Recall that the approximate time to
fully charge or fully discharge a capacitor is 5?
5RC. Example If R 1 kO and C 100 pF,
determine the time to fully charge or fully
discharge the capacitor. 5?
5RC 5(103)(100 x 10-12) 5 x 10-7 0.5 us
5
Lecture 9 EGR 262 Fundamental Circuits Lab
Charging a capacitor with an initial voltage,
Vo In general the complete response to an
RC circuit with DC sources has the form v(t)
B Ae-t/RC If the capacitor has an initial
voltage Vo and charges to the source voltage Vx
as shown below, then B and A can be evaluated
using the values of v(t) at t 0 and t ? v(?)
Vx B Ae-? B v(0) Vo B Ae0 B A,
so A Vo Vx so v(t) B Ae-t/RC v(?)
v(0) - v(?)e-t/RC or
v(t)
v(t) Vx Vo Vxe-t/RC
Vx
Vo
v(0) Vo
t
0
5? 5RC
0
Similarly, the lab manual shows
v(t) Vx Vo Vxe-t/RC
6
Lecture 9 EGR 262 Fundamental Circuits Lab
RC Circuit Response to a PWM signal If a PWM
signal is applied to an RC circuit as shown
below, the capacitor will charge during the
positive portion of the PWM cycle and will
discharge during the null (0) portion of the
cycle.
7
Lecture 9 EGR 262 Fundamental Circuits Lab
Determining the RC Circuit Response to a PWM
signal If 5RC is large compared to the period of
the PWM signal, the capacitor will discharge
little between pulses as illustrated below. Since
the initial change in an exponential response is
almost linear, the charging and discharging
capacitor voltage resembles a saw tooth
waveform as shown below.
The ripple voltage is often expressed as a
percentage of the mean, or average,
voltage. Example If Vm 10V, and Vr 0.5V,
then the ripple voltage is Vr/Vm100 5.
8
Lecture 9 EGR 262 Fundamental Circuits Lab
DAC used in Lab 5
DAC used in Lab 9
9
Lecture 9 EGR 262 Fundamental Circuits Lab
Comparison of DAC from Lab 5 and DAC Circuit
from Lab 9 The R-2R ladder network of Lab 5
will be replace by an RC circuit that will be
charged to the desired analog voltage where the
voltage will vary according to the duty cycle of
the PWM output developed in Lab 8.

• Advantages of PWM DAC
• Only 1 output from the MicroStamp11 is required
  (instead of 3 outputs for the 3-bit R-2R ladder
  network).
• 6 bits of precision will be generated (resulting
  in 64 analog output levels versus 8 analog output
  levels for the R-2R ladder network).
• Disadvantages of PWM DAC
• The analog output will not truly be a constant,
  but will have a ripple voltage.
• The response time to produce the analog outputs
  will be slower and will depend on the time
  constant, ?, of the RC circuit.

10
Lecture 9 EGR 262 Fundamental Circuits Lab
4.1. Pre-lab Tasks (1) Consider an RC circuit
whose input is a PWM signal with a period T and
pulse width T1 . Derive an equation for the
signals steady state value, Vm, and an equation
for the ripple voltage, Vr , as a function of R,
C, T1, and T (i.e., show the derivation of Eq. 5
and Eq. 6 in the class notes.) Show all steps.
11
Lecture 9 EGR 262 Fundamental Circuits Lab
Solving the two simultaneous expressions for V1
and V0 yields
and substitute these into the expressions for Vm
and Vr to show that
12
Lecture 9 EGR 262 Fundamental Circuits Lab
4.1. Pre-lab Tasks (continued) (2) Assume
that the PWM signal has a 50 percent duty cycle,
RC is 10 ms, and V 5V. Substitute these values
into Eq. 5 and Eq. 6 for Vm and Vr to find
expressions for Vm and Vr as a function of T
(i.e., show the derivation of Eq. 7 and Eq. 8 in
the class notes.)
Determine Vm and Vr as a function of T If D
50 0.5, then T1 0.5T. Show that
substituting RC 10 ms, V 5V, and T1 0.5T
into the expressions for Vr and Vm (Eq. 5-6)
yields
13
Lecture 9 EGR 262 Fundamental Circuits Lab
4.1. Pre-lab Tasks (continued) (3) Use Eq. 7
and Eq. 8 to calculate Vm , Vr and ripple as T
varies from 0.1ms to 3 ms (see sample table
below). If we want the maximum ripple voltage to
be 5, what value of T should be used? Highlight
this result in the table (it should be T 2 ms).
Add an explanation as to the significance of
this highlighted line in the table.
Finding T for a max ripple voltage of 5 Form
a table in Excel (similar to the one below) to
find the largest value of T such at the ripple
voltage is less than or equal to 5 (the result
should be T 2 ms). Let T vary from 0.1ms to
3ms.
T Vr Vm ripple
0.0001
0.0002
0.0003

0.0030
14
Lecture 9 EGR 262 Fundamental Circuits Lab
4.1. Pre-lab Tasks (continued) (4) Assume that
RC 10 ms, V 5V, and T 2ms (so that T1 DT
0.002T). Substitute these values into Eq. 5 to
find an expression for Vm in terms of D (i.e.,
derive Eq. 9).
Determine Vm as a function of duty cycle Using
the result from the last table (T 2ms), plot Vm
versus T1/T D (duty cycle). So, substituting V
5V, RC 10ms, T 0.002 and T1 0.002D into
Eq. 5, the expression for Vm is now
(5) Calculate the frequency, f, for T 2 ms.
15
Lecture 9 EGR 262 Fundamental Circuits Lab
4.1. Pre-lab Tasks (continued) (6) Form a table
calculating Vm as D varies from 0 to 100 in
increments of 5. Also graph Vm versus D. See
sample table and graph in class notes. What does
this plot suggest about the relationship between
the duty cycle, D, and the average steady-state
capacitor voltage?
Exploring the relationship between Vm and D
Use Excel to vary D from 0 to 100 in 5
increments and calculate Vm. Also graph the
results.
D Vm
0.00 0.00
0.05
0.10

1.00 5.00
You should find is that the average voltage
varies linearly with the duty cycle, D.
Therefore, we can vary the duty cycle of the PWM
output and create analog outputs that vary
linearly from 0V to 5V. This result is very
nice, but was not obvious!
16
Lecture 9 EGR 262 Fundamental Circuits Lab
4.1. Pre-lab Tasks (continued) (7) If RC 10
ms, form a table of 5 or more possible choices of
R and C values using the following
constraints A) 1 k? lt R lt 10 k? B) Use
standard 5 resistor values (see table in Pinouts
document on course website) C) Use capacitor
values available in lab (see table in Pinouts
document on course website) (8) Select one of the
combinations of RC values in the table above (and
highlight it) and draw a schematic of the RC
circuit connected to the MicroStamp11. (9) Program
Listing Modify the main program you wrote in
the preceding lab as follows A) Prompt the user
to enter a digital value (0-63) representing a
6-bit digital input. B) Convert the digital
value to a duty cycle (perhaps D x100/63)
before calling the setpwm function. (10) Program
Listing Modify kernel8.c (and save as
kernel9.c) changing T from 4 ms to 2 ms (i.e.,
change number of clock ticks from 9828 to 4914).
(11) Explanation of how the program and circuit
work.
17
Lecture 9 EGR 262 Fundamental Circuits Lab
4.2. In-lab Tasks (1) Measure R with an
ohmmeter and C with an impedance bridge and
record their values. Calculate RC and verify
that it is within 20 of the designed 10 ms
value. (2) Build the RC circuit and attach it to
pin PA4. (3) Verify that the circuit is working
properly. As the input varies from 0 to 63, the
output voltage should vary from 0V to 5V. Note
that the output may not be correct for 0 and 63,
but should work correctly for 1-62. (4) Create a
table for measuring the analog output, Vm, for 64
digital input values (shown in both decimal and
binary form) to be entered using the keyboard.
Use a DMM (set to measure DC voltages) to measure
the analog voltage output by your DAC circuit for
digital inputs of 0 to 63. See sample table
below.
Digital Input (decimal form) Digital Input (binary form) Analog Output (volts)
0 000000
1 000001

62 111110
63 111111
18
Lecture 9 EGR 262 Fundamental Circuits Lab
4.2. In-lab Tasks (5) Use the oscilloscope to
capture an image of the analog output voltage,
Vm, for at least 10 different digital inputs
between 1 and 62. Add cursors to the max and min
points on the waveform to measure the ripple
voltage. Note that it may be difficult to
stably trigger the scope directly from the RC
circuits output. It is recommended that you use
channel 1 to display the RC circuits output and
that you use channel 2 to display the PWM signal.
Be sure to trigger the scope from channel 2 as
the PWM signal provides a more reliable
triggering signal. See a sample screen capture
on the following slide. (6) Label each screen
capture with the digital input and the calculated
ripple voltage. (7) Include a printout from the
terminal program showing how the user interacts
with the program. (8) Description of what
happened during in-lab task.
19
Lecture 9 EGR 262 Fundamental Circuits Lab
Sample screen capture using WaveStar
20
Lecture 9 EGR 262 Fundamental Circuits Lab

• 4.3. Post-Lab Tasks
• (1) Include a listing of your ?nal program in
  the lab book and explain how it works.
• (2) Plot the measured analog voltages for
  digital inputs 1-62. Is the graph linear?
  Should it be?
• Plot ripple versus digital input. Use ripple
  (ripple voltage measured with screen
  capture)/2.5100. What is the max ripple?
  Does this match the design specifications?
• Discuss the performance of the DAC.
• (5) Compare the DAC constructed in this lab to
  the one built using an R2R ladder network in Lab
  5.