Time Modelling and Data Flow Descriptions

1

• bus
• waveforms
• Transport and inertial delay
• Assignment statements
• more on Variables and signals
• delta and simulation
• How VHDL simulator works

2
This lecture is very important

• This lecture is very important.
• You can learn syntactical aspects from manual but
  here we discuss the principle of how the
  simulator works.
• Therefore we will show many examples and will
  discuss some aspects several times from different
  points of view.
• Please make sure that you really understand all
  concepts here.

3
Event Driven Simulation and the first encounter
with delta
4
Simulation Loop is based on executing signals
from time queue
5
Process Triggering
6
Some Rules for Processes

• These rules have to be remembered. Our next
  slides will explain better why it is so

7
An Infinite Loop

• Remember processes repeat indefinitely with new
  data coming. But here is not new data

8
A Common Error of users

• It is safe to add all input signals from your
  circuit to the sensitivity list. You may only
  slow down the simulator.

9
Delta Time
10
Two-Dimensional Time
11
A Delta-Time Infinite Loop

• This is wrong way to make a clock.

12
Behavioral Modeling in VHDL

• VHDL behavior
• Sequential Statements
• Concurrent Statements

These are two fundamental behaviors from which
all simulation and synthesis models work
13
VHDL behavior models
concurrent
sequential
14
Sequential v.s. Concurrent Statements

• VHDL is inherently a concurrent language
• All VHDL processes execute concurrently
• Concurrent signal assignment statements are
  actually one-line processes
• Processes are re-executed if any signal in its
  sensitivity list is changed
• VHDL statements execute sequentially within a
  process
• Concurrent processes with sequential execution
  within a process offers maximum flexibility
• Supports various levels of abstraction
• Supports modeling of concurrent and sequential
  events as observed in real systems

15
VHDL behavior Concurrent, sequential and
processes
16
Concurrent Statements
17
Concurrent Statements

• Basic granularity of concurrency is the process
• Processes are executed concurrently
• Concurrent signal assignment statements are
  one-line processes
• Mechanism for achieving concurrency
• Processes communicate with each other via signals
• Signal assignments require delay before new value
  is assumed
• Simulation time advances when all active
  processes complete
• Effect is concurrent processing
• i.e. order in which processes are actually
  executed by simulator does not affect behavior
• Other than in last slide Concurrent VHDL
  statements include
• Block, process, assert, component instantiation

18
Processes
19
Behavioral sequential statements
20
What specifically are the sequential statements?
21
Initialization of processes
22
Execution of parallel processes

• The processes here have no sensitivity list but
  have wait statements

23
Model of Processes waiting for events to occur
24
Signals and variables in Processes
25
Communication Between Processes via Signals
These are executed when first process allows
26
All these assignments executed in no time
Many assignment Statements D ? 1 Many assignment
statements
Wait until D1
Wait 10nS
Diagrams like this are useful to visualize time
in processes and how they interact
Process FIRST
Process NEXT
27
Another example
A lt 8 V1
D ? 1
Wait until D1
Wait 10nS
From next iteration of process NEXT
D ? 0
V ? 0
Wait 10nS
From first iteration of process NEXT
Process NEXT
Process FIRST
Wait 2nS
0
2
10
D1 A8 V1 -gt 0
D1 A8 V0
D0 A8 V1
From next iteration of process NEXT
28
V0
D1
2nS
A8,V1
10nS
10nS
D0
29
Signals Communicate in Between the Processes
signals propagate when processes are waiting
Signals propagate within processes and between
processes!
30
Signals Assigned After Processes Run waiting
processes can awake another processes
31
Example of role of WAIT in a process
Assignment of value to signal C will be discussed
in next slides
No delay of elements
Observe that there is no sensitivity list here.
When A or B change, new value of variable TEMP
is immediately calculated. It is used to
calculate output signal C, not shown. This is
just a trivial example. More will come.
32
Process with Signals
33
Sensitivity List
It is important to understand that change of c
will not initiate the process here!
34
Process with Sensitivity List
We declare arbitrary delays
You can use variables to simplify description or
define exact timing
35
Compilation and Simulation of VHDL Code

• Compiler (Analyzer) checks the VHDL source code
  
• does it conforms with VHDL syntax and semantic
  rules
• are references to libraries correct
• Intermediate form used by a simulator or by a
  synthesizer
• Elaboration
• create ports, allocate memory storage, create
  interconnections, ...
• establish mechanism for executing of VHDL
  processes

compilation
Internal data structures
synthesis
36
VHDL Modeling Concepts

• Semantics (meaning) of VHDL is heavily based on
  SIMULATION
• A design is described as a set of interconnected
  modules
• A module could be another design (component) or
  could be described as a sequential program
  (process)

37
VHDL Program Structure visualization of
concurrency
These modules are simulated concurrently through
signals This means that they are all simulated
in the same time before next delta comes
38
A general VHDL design with modules another
visualization of concurrency
Entity is End entity
I1
O1
I2
IO1
s1
component
concurrent assignment
I1
O1
s2
architecture of is ... begin end
s3
s4
s8
s9
s6
process 1
process 2
concurrent assignment
I2
IO1
s5
s7
This diagram helps to visualize how process
communication works - concurrency
39
VHDL Simulator
start
Init t 0
more event
stop
get earliest event
delta delay
advance time
update signals
This diagram helps to visualize how process
communication works - concurrency
execute triggered processes
during process execution, new events may be added
40
Process Statements

• FORMAT
• PROCESS_LABEL process
• -- declarative part declares functions,
  procedures, types, constants, variables, etc
• begin
• -- Statement part
• sequential statement
• sequential statement
• wait statement -- eg. Wait for 1 ms or wait on
  ALARM_A
• sequential statement
• wait statement
• end process

Flow of control
This diagram helps to visualize how process
communication works - concurrency
41
Modeling Timing in VHDL

• VHDL can be used to specify different aspects of
  timing characteristics of hardware devices
• propagation delay of signals
• operational time
• Why we need timing?
• The type time is a pre-defined physical type.
• Mainly useful for modeling device timing
  characteristics
• Can also be used to specify timing requirements,
  e.g., setup and hold times of devices.
• You can parameterize timing properties of an
  entity.

42
EXAMPLE Process Declaration of Clock Generator
Clock_gen process (clk) is begin if clk
0 then clk lt 1 after T_pw, 0
after 2T_pw endif end process clock_gen
2T_pw
T_pw
43
Waveform and Driver

• Simulator uses drivers for signals
• A driver of a signal contains a current value and
  a waveform representing projected future values.
• Waveform elements are appended to a driver
  whenever a signal assignment is executed.

How to describe a waveform? Use after
44
Using Nested IFs and ELSEIFs
Simulator has also to understand semantics of
statements like IF
Advise is to draw yourself flowchart like this to
understand better
45
What Happens in Simulation?
After examples discussed, we now understand
better what are events and how they are
scheduled. Details of implementation are not
important at this time.
46
Timing Model in VHDL
47
Timing Model in VHDL

• VHDL uses a simulation cycle to model the
  stimulus and response nature of digital hardware

We will introduce 3 models for delay
Start Simulation
Delay
Execute Processes
Update Signals
End Simulation
48
Types of Delay in VHDL

• All VHDL signal assignment statements prescribe
  an amount of time that must transpire before the
  signal assumes its new value
• This prescribed delay can be in one of three
  forms
• Transport -- prescribes propagation delay only
• Inertial -- prescribes minimum input pulse width
  and propagation delay
• Delta -- the default if no delay time is
  explicitly specified

Input
Output
delay
49
Concepts of Delays and Timing

• The time dimension in the signal assignment
  refers to simulation time in a discrete event
  simulation
• There is a simulation time clock
• When a signal assignment is executed, the delay
  specified is added to current simulation time to
  determine when new value is applied to signal
• Schedules a transaction for the signal at that
  time

output
input
50
More on inertial and transport models

• Inertial delay
• Model the time lag between stable inputs and
  valid output of a device
• Representative of combinational logic elements
• Pulses smaller than transmission delay are
  suppressed
• Default model for VHDL descriptions
• Transport delay
• Model a pure delay mechanism
• All pulses are transmitted
• Used for transmission lines or elements with
  clock- cycle latency

51
Inertial versus transport delay

• How small should be the glitch to be
  distinguished by inertial and transport?

We will answer in next slides
Observe the spike is lost in A when we use AFTER
Observe the spike is NOT lost in B when we use
TRANSPORT
52
Transport Delay
Under this model, ALL input signal changes are
reflected at the output

• Delay must be explicitly specified by user
• Keyword TRANSPORT must be used
• Signal will assume its new value after specified
  delay

-- TRANSPORT must be specified Output lt
TRANSPORT NOT Input AFTER 10 ns
As we see, spikes are not lost
0 5 10 15 20 25 30 35
53
Specifying Delays Inertial Model

• Inertial Delay Model
• reflects physical inertia of physical systems
• glitches of very small duration not reflected in
  outputs
• SIG_OUT lt not SIG_IN after 7 nsec --implicit
• SIG_OUT lt inertial ( not SIG_IN after 7 nsec )
• Logic gates exhibit lowpass filtering

3 ns
10ns
SIG_IN
2ns
SIG_OUT
9 ns
19 ns
54
Inertial Delay

• Provides for specification of input pulse width,
  i.e. inertia of output, and propagation delay
• Inertial delay is default and REJECT is optional

target lt REJECT time_expression INERTIAL
waveform
Output lt NOT Input AFTER 10 ns -- Propagation
delay and minimum pulse width are 10ns
Here reject is not used
Here we do not write INERTIAL because it is a
default. Signal shorter than 10ns is avoided
0 5 10 15 20 25 30 35
55
Inertial Delay with REJECT

• Note that REJECT feature is new to VHDL 1076-1993

• Example of gate with inertia smaller than
  propagation delay
• e.g. Inverter with propagation delay of 10ns
  which suppresses pulses shorter than 5ns

Output lt REJECT 5ns INERTIAL NOT Input AFTER
10ns
Example of gate with inertia smaller than
propagation delay e.g. Inverter with propagation
delay of 10ns which suppresses pulses shorter
than 5ns
Input
Output
0 5 10 15 20 25 30
35
Because here we clearly specify REJECT 5ns, only
signals 5ns or shorter are rejected and 7ns is
not rejected
56
A problem with inertial delay

• Output has propagation delay of 4ns

buffer
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58

• How the simulator works.
• Delta

59
Delta Delay

• Delta Delay is the default signal assignment
  propagation delay in case that no delay is
  explicitly prescribed
• VHDL signals assignment cannot take place
  immediately
• Delta is an infinitesimal VHDL time unit so that
  all signal assignments can result in signals
  assuming their values at some future time
• E.g.
• Delta delay supports a model of concurrent VHDL
  process execution
• Order in which processes are executed by
  simulator does not affect simulation output

Output lt NOT Input -- Output assumes new value
in one delta cycle
60
Delta DelayAn Example without Delta Delay

• What is the behavior of C?

A
IN 1-gt0
C
We do not like such idea of simulator
B
1
AND gate evaluated first IN 1-gt0 A 0-gt1 C
0-gt1 B 1-gt0 C 1-gt0
NAND gate evaluated first IN 1-gt0 A 0-gt1 B
1-gt0 C 0-gt0
Glitch generated
61
Delta DelayAn Example with Delta Delay

• What is the behavior of C?

A
IN 1-gt0
C
B
1
Using delta delay scheduling
Time Delta Event 0 ns 1 IN
1-gt0 eval INVERTER 2
A 0-gt1 eval NAND, AND
3 B 1-gt0 C 0-gt1
eval AND 4 C
1-gt0 1 ns
Gates that are successors of gate that changed
signal value are evaluated
62
Time modelling- delta delay .1. What is wrong
with old simulators?
Clock changes from 0 to 1
As we see in this example the result of
simulation depends on order of evaluating gates.
This is bad.
AND first evaluation
NAND first evaluation

• With this order of evaluation a glitch in signal
  D is created which means clocking
• One more clock is generated - this is bad.

As we see, timing behavior simulated depends on
the gate evaluation order
This is good
again
63
Time modelling- delta delay . Delta delay of VHDL
solves the problem.
This is levelized evaluation from inputs to
outputs

• Many delta units of time passed but only one unit
  of time reported to the user

delta
Delta is as close to zero as we want
64
Delta Delay instability time
This example shows use of delta to simulate
latch. Here delay is declared using after

• If no delay time is specified, a delta delay is
  assumed for any signal assignment.
• Delta delay represents an infinitesimal delay,
  less than any measurable time (i.e.,
  femtoseconds), but still larger than zero.
• An example

5ns
Black are instability times
These are moments of time
65
Signals vs Variables signal used for Out_1

• A key difference between variables and signals is
  the assignment delay

ARCHITECTURE sig_ex OF test IS SIGNAL a, b, c,
out_1, out_2 BIT BEGIN PROCESS (a, b, c,
out_1) BEGIN out_1 lt a NAND b out_2 lt
out_1 XOR c END PROCESS END sig_ex
signal
time
a b c
out_1
out_2
Symbol d represents delta
1
0
1d
12d
66
Signals vs Variables (Cont.) Variable used for
out_3
ARCHITECTURE var_ex OF test IS SIGNAL
a,b,c,out_4 BIT BEGIN PROCESS (a, b,
c) VARIABLE out_3 BIT BEGIN out_3 a
NAND b out_4 lt out_3 XOR c END PROCESS END
var_ex
variable
Out_3 is a variable so the change is immediate as
shown by red arrow
Time a b c out_3 out_4 0 0 1 1
1 0 1 1 1 1 0 0 1d 1 1
1 0 1
a b c
This example has no any other meaning, it just
has to explain the timing of variables and
signals in a simulator
a,b,c,out_4 are signals but out_3 is a variable
out_3
out_4
1
0
1d
67
Delta Delay and the simulator in more detail

• If no future time is specified, VHDL
  automatically assumes a small time delay.
• This delay is the delta delay.
• The smallest unit of time i.e. 0 fs.
• Delta causes changes to occur only in the future
• Delta is consistent with the definition of
  signals.
• Mechanism
• Assignment schedules a transaction
• The transaction is applied after the process
  suspends.
• Process does not see the effect until it resumes
  next time.

68
How it works?

• Recollect simulator kernel.
• Two phases
• Signal update phase
• Process execution phase.
• Signal update phase updates the values of the
  signals at the current simulation time.
• This may trigger events.
• Process execution phase responds to the events
  and they execute.

69
Why Delta Delay?

• Assignments are done in the process execution
  phase. Eg. X lt 10
• Transaction is not applied immediately.
• It can be done only in the signal update phase.
• When all processes are suspended, simulation time
  is updated.
• Only now is the transaction applied.

70
Simulation Cycle RevisitedSequential vs
Concurrent Statements

• VHDL is inherently a concurrent language
• All VHDL processes execute concurrently
• Concurrent signal assignment statements are
  actually one-line processes
• VHDL statements execute sequentially within a
  process
• Concurrent processes with sequential execution
  within a process offers maximum flexibility
• Supports various levels of abstraction
• Supports modeling of concurrent and sequential
  events as observed in real systems

71
This example will illustrate simulating a 4-bit
Adder
72
Here is the structural description of 4-bit Adder
73
4-bit Adder Simulation and analysis of deltas
74
Next example will show Modeling Flip-Flops Using
VHDL Processes

• Whenever one of the signals in the sensitivity
  list changes, the sequential statements are
  executed in sequence one time

General form of process
75
JK Flip-Flop Model
Animation and details in next slide
76
Notes to the JK Flip-Flop Model
77
Another simulation example to Recall on Delta
Delay

• Default signal assignment propagation delay if no
  delay is explicitly prescribed
• VHDL signal assignments do not take place
  immediately
• Delta is an infinitesimal VHDL time unit so that
  all signal assignments can result in signals
  assuming their values at a future time
• E.g.
• Supports a model of concurrent VHDL process
  execution
• Order in which processes are executed by
  simulator does not affect simulation output

Output lt NOT Input -- Output assumes new value
in one delta cycle
78
Simulation Example illustrating delta
Queue for A
Queue for B
79
Illustration of force and timing diagram in
Simulation of the VHDL Model
All forced signals here
Simulation command file
Force clk
Force X
Waveforms
80
Structural Model of State Machine
Package bit_pack is a part of library BITLIB
includes gates, flip-flops, counters
81
Simulation of the Structural Model
Simulation command file
Waveforms
82
One More Simulation Example gate timing
Continued
83
VHDL simulation of gates with delays

• From force

84
The same circuit but another description for
simulation
Now simulator reacts to changes of si signals

• Order does not matter because we are in
  architecture and we are executing concurrent
  statements and not inside a process!

85
Now we see internal delays
86
Third description of this example
Change of si creates no event for this process
87
Differences between CSA and Process
Change of out1, out2 repeats simulation
Change of out1, out2 does not repeat simulation
88
Signals and Variables
X is signal
X is variable
X is variable so changes immediately and next
equation takes new value and not old value as in
the code from the left
89
Variables

• Can be altered using variable assignment
  statements
• Updating takes place immediately
• Can be declared only within Processes and
  Functions
• Variables Inside Processes
• Variables inside processes are static
• Assigned value is stored till next call.
• Variables inside functions and procedures are not
  static

90
Signals

• Represent data values on physical lines in
  circuits.
• Models the response in actual circuits accurately
• Does not change values immediately.
• Assignment does not affect the value immediately.
• Always occurs sometime in the future can be at
  the same simulation time though.
• Future time at which signal is affected can be
  explicitly stated. Waveform can also be
  specified.

91

• Variable assignment statement
• Signal assignment
• wait

92
Sequential Statements

• Variable assignment statement
• Signal assignment
• If statement
• Case statement
• Loop statement
• Next statement

• Exit statement
• Null statement
• Procedure call statement
• Return statement
• Assertion statement

93
Variable assignment statement
Variable_assignment_statement
targetexpression architecture RTL of
VASSIGN is signal A, B, J bit_vector(1
downto 0) signal E, F, G bit
begin p0 process (A, B, E, F, G, J)
variable C, D, H, Y bit_vector(1
downto 0) variable W, Q
bit_vector(3 downto 0) variable
Z bit_vector(0 to 7)
variable X bit
variable DATA bit_vector(31 downto 0)
begin ... end process
end RTL
We declare various types of variables inside the
process
94
Variable assignment statement
signal A, B, J bit_vector(1 downto 0) signal
E, F, G bit

• p0 process (A, B, E, F, G, J)
• -- A, B, J, D, H bit_vector --
  E, F, G bit
• begin
• C "01"
• X E nand F
• Y H or J
• Z(0 to 3) C D
• Z(4 to 7) (not A) (A nor B)
• D ('1', '0')
• W (2 downto 1 gt G, 3 gt '1',
  others gt '0')
• DATA (others gt '0')
• end process

Variable assigned to a signal
The same signal G (a bit) goes to two bits
concatenation
Make note of mapping notation.. Bit G assigned to
two bits.
Here we assign signals to variables
95
Formal Syntax of a signal assignment statement
VHDL syntax description in metalanguage

• Signal_assignment_statement
• targetlttransportwaveform_element,waveform_ele
  ment
• waveform_element
• value_expressionafter time_expressionnullafte
  r time_expression

96
Perhaps the most difficult to understand
statement of VHDL.If you do not understand it ,
you will have troubles to interpret timing
results from simulation and you will be not able
to do good behavioral descriptions

• WAIT STATEMENT AND TIMING

97
WAIT statement
Three types of WAIT
Common student mistake, may be because of syntax
mistake
98
Example of WAIT statement
99
The wait statement
100
Equivalent Processes
101
Wait Until and Wait for
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103
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104
Signal Declarations

• Signals must not be declared inside a process or
  subprogram.
• Ports must always be signals.
• Models sub-system communication correctly.

105
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106
Example Variables vs signals

• Signal X is changing outside the process, not
  shown how.

107
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108
Wait Statements

• ... an alternative to a sensitivity list
• Note a process cannot have both wait
  statement(s)and a sensitivity list
• Generic form of a process with wait statement(s)

• How wait statements work?
• Execute seq. statement until a wait statement is
  encountered.
• Wait until the specified condition is satisfied.
• Then execute the next set of sequential
  statements until the next wait statement is
  encountered.
• ...
• When the end of the process is reached start over
  again at the beginning.

process begin sequential-statements wait
statement sequential-statements wait-statement
... end process
109
Forms of Wait Statements
wait on sensitivity-list wait for
time-expression wait until boolean-expression

• Wait on
• until one of the signals in the sensitivity list
  changes
• Wait for
• waits until the time specified by the time
  expression has elapsed
• What is thiswait for 0 ns

• Wait until
• the Boolean expression is evaluated whenever one
  of the signals in the expression changes, and the
  process continues execution when the expression
  evaluates to TRUE

110
Signal assignment statements and wait for

• p0 process (A, B)
• begin
• Y lt A nand B after 10 ns
• X lt transport A nand B after 10 ns
• end process
• p1 process
• begin
• A lt '0', '1' after 20 ns, '0' after 40 ns,
  '1' after 60 ns
• B lt '0', '1' after 30 ns, '0' after 35 ns,
  '1' after 50 ns
• wait for 80 ns
• end process

Switching time of circuit p0
80nS
A
B
X
Y
A pulse with a duration shorter than the
switching time of the circuit (10nS) will be
transmitted in transport.
Recall waveforms , transport and inertial delay.
Recall that default is intertial, as shown for
signal X
111
Signal assignment statement
A pulse (5 nS) with a duration shorter than the
switching time of the circuit (10nS) will be
transmitted in transport.
Inertial and Transport Delays
112

• p1 process
• begin
• A lt '0', '1' after 20 ns,
• '0' after 40 ns, '1' after 60 ns
• B lt '0', '1' after 30 ns,
• '0' after 35 ns, '1' after 50 ns
• wait for 80 ns
• end process
• end RTL

• entity DELAY is
• end DELAY
• architecture RTL of DELAY is
• signal A, B, X, Y bit
• begin
• p0 process (A, B)
• begin
• Y lt A nand B after 10 ns
• X lt transport A nand B after 10 ns
• end process

X
Y
113
Role of wait for in discarding signals
Waiting 30ns to start next assignment
Waiting 50ns to start next assignment. 30 50
80
30ns
20ns

• entity DRIVER is
• end DRIVER
• architecture RTL of DRIVER is
• signal A integer
• begin
• pa process
• begin

• A lt 3, 5 after 20 ns, 7 after 40 ns, 9 after 60
  ns
• wait for 30 ns
• A lt 2, 4 after 20 ns, 6 after 40 ns, 8
  after 60 ns
• wait for 50 ns
• end process
• end RTL

Discarded by the end of first assignment to A
Discarded by the end of the second assignment to
A. Time 305080 has passed
This slide explains the role of wait for to
discard part of assignment statement
114
Differences between variables and signals
There are differences where declared and when
updated

• 1. Where declared
• Local variables are declared and only visible
  inside a process or a subprogram.
• Signals cannot be declared inside a process or a
  subprogram.
• 2. When updated
• A local variable is immediately updated when the
  variable assignment statement is executed.
• A signal assignment statement updates the signal
  driver.
• The new value of the signal is updated when the
  process is suspended, as shown in last slide.

115
Signal assignment statement
Differences between variables and signals

• 3. Variables are cheaper to implement in VHDL
  simulation since the evaluation of drivers is not
  needed.
• Variables require less memory.
• 4. Signals communicate among concurrent
  statements.
• Ports declared in the entity are signals.
• Subprogram arguments can be signals or variables.
• 5. A signal is used to indicate an interconnect
  (net in a schematic).
• A local variable is used as a temporary value in
  a function description.

116
Signals versus variables

• 6. A local variable is very useful to factor out
  common parts of complex equations to reduce the
  mathematical calculation.
• 7. Right-hand sides
• The right-hand side of a variable assignment
  statement is an expression.
• There is no associated time expression.
• The right-hand side of a signal assignment
  statement is a sequence of waveform elements with
  associated time expressions.

117
Signals and variables in timing diagrams

• entity SIGVAL is
• port (
• CLK, D in bit
• FF2, FF3 out bit
• Y out bit_vector(7 downto 0))
• end SIGVAL
• architecture RTL of SIGVAL is
• signal FF1, SIG0, SIG1 bit
• begin
• p0 process (D, SIG1, SIG0)
• variable VAR0, VAR1 bit

Variables and signals on left
begin VAR0 D VAR1 D
SIG0 lt VAR0 SIG1 lt VAR1 Y(1
downto 0) lt VAR1 VAR0 Y(3 downto 2) lt
SIG1 SIG0 VAR0 not VAR0 VAR1
not VAR1 SIG0 lt not VAR0 SIG1
lt not D Y(5 downto 4) lt VAR1 VAR0
Y(7 downto 6) lt SIG1 SIG0 end process
Variables and signals on right
118
Timing of variables versus timing of signals
FF2 is old value of FF1 according to signal
semantics

• p1 process
• begin
• wait until CLK'event and CLK '1'
• FF1 lt D FF2 lt FF1
• end process
• p2 process
• variable V3 bit
• begin
• wait until CLK'event and CLK '1'
• V3 D FF3 lt V3
• end process
• end RTL

CLK D VAR0 VAR1 SIG0 SIG1 Y FF1 FF2 V3 FF3

• Variable V3 changes at the same time as FF1, and
  so FF3
• FF3 unlike FF2

MORAL Signals are scheduled, variables change
immediately
119
WAIT
p0 process (D, SIG1, SIG0 variable VAR0, VAR1
bit begin VAR0 D VAR1 D
SIG0 lt VAR0 SIG1 lt VAR1 Y(1
downto 0) lt VAR1 VAR0 Y(3 downto 2) lt
SIG1 SIG0 VAR0 not VAR0 VAR1
not VAR1 SIG0 lt not VAR0 SIG1
lt not D Y(5 downto 4) lt VAR1 VAR0
Y(7 downto 6) lt SIG1 SIG0 end process

• p1 process
• begin
• wait until CLK'event and CLK '1'
• FF1 lt D FF2 lt FF1
• end process

var0
p2 process variable V3 bit begin
wait until CLK'event and CLK '1' V3
D FF3 lt V3 end process end RTL
120
Using FF1, a signal, the old value is substituted
Using V3, a variable, the new value is substituted

• p1 process
• begin
• wait until CLK'event and CLK '1'
• FF1 lt D FF2 lt FF1
• end process
• p2 process
• variable V3 bit
• begin
• wait until CLK'event and CLK '1'
• V3 D FF3 lt V3
• end process
• end RTL

CLK D VAR0 VAR1 SIG0 SIG1 Y FF1 FF2 V3 FF3
Compare FF2 (from signal change) and FF3 (from
variable change)
121

• p1 process
• begin
• wait until CLK'event and CLK '1'
• FF1 lt D FF2 lt FF1
• end process

p2 process variable V3 bit begin
wait until CLK'event and CLK '1' V3
D FF3 lt V3 end process end RTL
p0 process (D, SIG1, SIG0) variable VAR0, VAR1
bit begin VAR0 D VAR1 D
SIG0 lt VAR0 SIG1 lt VAR1 Y(1
downto 0) lt VAR1 VAR0 Y(3 downto 2) lt
SIG1 SIG0 VAR0 not VAR0 VAR1
not VAR1 SIG0 lt not VAR0 SIG1
lt not D Y(5 downto 4) lt VAR1 VAR0
Y(7 downto 6) lt SIG1 SIG0 end process
SIG0 changes with D, no delay, in process 1 D,
SIG0 and SIG1 are in sensitivity list
FF1 takes old D
V3 takes new D
Input signals
122
Three architectures

• variable V integer
• begin
• V (BC DEF G)
• Y lt A V Z lt A - V
• end process
• end RTL1
• architecture RTL2 of TEMP is
• signal A, B, C, D, E, F, G, Y, Z integer
• signal V integer
• begin
• p0 process (A, B, C, D, E, F, G)
• begin
• V lt (BC DEF G)
• Y lt A V Z lt A - V
• end process
• end RTL2

v calculated immediately
The same statements

• entity TEMP is
• end TEMP
• architecture RTL of TEMP is
• signal A, B, C, D, E, F, G, Y, Z integer
• begin
• p0 process (A, B, C, D, E, F, G)
• begin
• Y lt A (BC DEF G)
• Z lt A - (BC DEF G)
• end process
• end RTL
• architecture RTL1 of TEMP is
• signal A, B, C, D, E, F, G, Y, Z integer
• begin
• p0 process (A, B, C, D, E, F, G)

Uses old value of v, because it is a signal
First architecture has no variables Second
architecture uses variable V Third architecture
uses additional signal V Their operation is
different because signal V is scheduled and
variable immediately assigned
123
Signal Declarations

• Signals must not be declared inside a process or
  subprogram.
• Ports must always be signals.
• Models sub-system communication correctly.

124
Signals - Drivers

• Value holder for a signal.
• Created when signal assignments schedule some
  value at some future time.
• Every signal has a separate driver.
• Can be thought of as a source for a signal.
• Driver maintains an ordered list of transactions.
• Recollect transaction is assignment made to a
  signal.
• Simulator uses the value of the signal stored in
  the driver.

125
Multiple Drivers

• Signals may be updated in more than 1 process at
  the same time.
• There may be more than 1 driver for the same
  signal, one for each process.
• The values assigned may be same or different.
• What to do if the values are different?

126
Multiple Drivers - Resolution

• ?? Resolution function is the solution.
• ?? This function resolves the value of the
  signal.
• ?? This function must resolve all possible pairs
  of values that two drivers may assign.
• ?? The signal being resolved is called the
  resolved signal.
• ?? The resolution function can be attached to
• ?? A signal directly or
• ?? A data-type itself.

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129
Homework Problem 1

• Using the labels, list the order in which the
  following signal assignments are evaluated if in2
  changes from a '0' to a '1'. Assume in1 has been
  a '1' and in2 has been a '0' for a long time, and
  then at time t in2 changes from a '0' to a '1'.

entity not_another_prob is port (in1, in2 in
bit a out bit) end not_another_prob   archite
cture oh_behave of not_another_prob is signal b,
c, d, e, f bit begin L1 d lt not(in1) L2
clt not(in2) L3 f lt (d and in2) L4 e
lt (c and in1) L5 a lt not b L6 b lt e
or f end oh_behave
130
Homework Problem 2

• Under what conditions do the two assignments
  below result in the same behavior? Different
  behavior? Draw waveforms to support your answers.

out lt reject 5 ns inertial (not a) after 20
ns out lt transport (not a) after 20 ns
131
X. Sharon Hu Bob Reese Shankar Balachandran
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