Introduction To Embedded System Design

1
Introduction To Embedded System Design
Name of University - Class Title
Embedded Systems Architecture A Comprehensive
Guide for Engineers and Programmers - An Elsevier
Science Publication
2
Overview

• What is an Embedded System?
• Embedded Systems Design
• Embedded Systems Design Development Lifecycle
  Model
• What is an Embedded Systems Architecture?
• The 6 Stages of Creating an Embedded
  Architecture.
• Stage 1 Have a Strong Foundation
• Know Your Standards
• Embedded Software
• Putting It All Together
• Stages 2-6 of Creating an Architecture

3
What Is An Embedded System ?

• A type of computer system.
• Some of the Most Common Traditional Definitions
• Embedded systems are more limited in hardware
  and/or software functionality then the PC.
• An embedded system is designed to perform a
  dedicated function
• Why dont these definitions entirely apply,
  today?

4
What is an Embedded System Continued?

• Automotive
• i.e. Ignition Systems, Engine Control, Antilock
  Braking System,
• Consumer Electronics
• i.e. TVs, STBs, appliances, toys, automobiles,
  cell phones
• Industrial Control
• i.e. robotics, control systems
• Medical
• i.e. Infusion Pumps, Dialysis Machines,
  Prosthetic Devices,Cardiac Monitors,
• Networking
• i.e. routers, hubs, gateways,
• Office Automation
• i.e. fax machines, photocopiers, printers,
  monitors,
• Aside from being types of computer systems,
  there is no single definition or characterization
  of embedded systems reflecting them all.

5
Embedded Systems Design
Phase 1 Creating The Architecture
Product Concept
Phase 2 Implementing the Architecture
Preliminary Requirements Analysis
Creation of Architecture Design
Phase 3 Testing the System
Phase 4 Maintaining the System
Develop Version of Architecture
Deliver Final Version of Architecture
Deliver Version of Architecture
Incorporate Feedback
Develop Implement the System
Review Obtain Feedback
Incorporate Feedback
Review and Test the System

• Embedded Systems Design and Development Lifecycle
  Model

Deliver Maintain the System
6
What is Embedded Systems Architecture?

• An abstraction of the embedded device that
  represents the
• embedded system as some combination of
  interacting elements.
• - physically represented as structures
• - many types of structures
• Layered, Kernel, Decomposition,
  Client/Server, Process,
• Sum of Structures Embedded Architecture
• Why care about the architecture of an embedded
  system?

7
6 Stages of Creating an Embedded Architecture

• Many industry popular methodologies for creating
  architectures (adaptable to embedded systems)
• Rational Unified Process (RUP), Attribute Driven
  Design (ADD), Object Oriented Process (OOP),
• More Pragmatic Approach the best of all worlds
• Stage 1 Having a Solid Technical Base
• Stage 2 Understanding the ABCs of Embedded
  Systems
• Stage 3 Defining the Architectural Patterns
  Reference Models
• Stage 4 Creating the Architectural Structures
• Stage 5 Documenting the Architecture
• Stage 6 Analyzing Evaluating the Architecture

8
Stage 1 Having a Strong Technical Base
Stanford University - EE109
9
Embedded Systems Model
Embedded System
10
EE109 Platform and the Embedded Systems Model
11
Know Your Standards

• Market Specific
• Consumer Electronics, Medical, Industrial
  Automation Control, Networking
  Communications, Automotive, Aerospace Defense,
  Office Automation,
• General Purpose
• Networking, Programming Language, Security,
  Quality Assurance,

12
How can a Programming Language Spec Add to An
Embedded Systems Architecture ?

• Translating Code
• Interpretation, Just-in-Time (JIT),
  Way-Ahead-of-Time (WAT)/Ahead-of-Time (AOT)
• Garbage Collection
• Copying, MarkSweep, Generational,

13
Translation of Code on Host Compiling
14
Translation of Code on Target
Interpretation
vtab
Byte Code 1
Interpretation
Source File (s)
Byte Code 2
Byte Code 2 Parsing
Byte Code 3
Compiler
Byte Code 2 Interpreting
Host
.
Byte Code File (s)

Way-Ahead-of-Time/Ahead-Of-Time WAT/AOT
1
vtab
JVM WAT Compiler
.class File
Byte Code 1
Compiled Byte Code 1
Byte Code 1
object File
Byte Code 2
Byte Code 2 Parsing Interpreting
Compiled Byte Code 2
Byte Code 2
2
Just-In-Time JIT
JVM Linker
Byte Code 3
Compiled Byte Code 3
Byte Code 3
Byte Code 2 JIT Compiling
Runtime Libraries
.

.
executables

2nd and Additional Passes of Processing Byte
Code
First Pass of Processing Byte Code
15
Garbage Collection Copying
16
Garbage Collection MarkSweep
17
Garbage Collection Generational
Older Generation Mark
(Sweep) Compact GC
Memory Before GC
Memory After GC Mark Sweep
Mark,Sweep, Compact Garbage Collector
Object 1
Object 1
?
? Mark
Object 2
Object 2
?
Object 3
Sweep
Object 4
Object 4
?
Memory After GC Compaction
Compact
Object 1
Object 2
Object 4
18
How can Java Add to An Embedded Systems
Architecture ?

• Embedded Java
• Standards (pJava, J2ME, Embedded Java, )
• Processing Bytecode (Interpretation, JIT,
  WAT/AOT)
• Garbage Collection (Copying, MarkSweep, )

19
How can .NetCE Add to An Embedded Systems
Architecture ?

• .NetCE Compact Framework
• Standard Common Language Specification
• Processing Bytecode (Interpretation/JIT)
• Garbage Collection ( Generational)

20
How can Scripting Languages Add to An Embedded
Systems Architecture ?

• Scripting Languages
• Perl, JavaScript, HTML,
• Processing Bytecode (Interpretation)

21
How can Networking Add to an Embedded Systems
Architecture ?
22
Open Systems Interconnection (OSI) Model
23
Networking Layers
Application Layer
Application Layer
Layer 7
Layer 7
Application Presentation Session Transport Ne
twork Data Link Physical
Presentation Layer
Presentation Layer
Session Layer
Session Layer
Transport Layer
Transport Layer
Network Layer
Network Layer
Data Link Layer
Data Link Layer
Layer 1
Layer 1
Physical Layer
Physical Layer
Transmission Medium
24
OSI and Real-World Networking Models TCP/IP
25
OSI and Real-World Networking Models WAP
26
OSI and Real-World Networking Models Bluetooth
27
OSI Layer 1 Physical Layer
28
Physical Layer Processing
Device 1
Device 2


Data Link Layer
Layer 2
Layer 2
Data Link Layer
1001110101110
0111010111001
Transmission Medium
Layer 1
Physical Layer
Layer 1
Physical Layer
29
OSI Layer 2 Data-Link Layer
Application Software Layer
System Software Layer
WAN
LAN
Wireless
Wired
Wireless
Wired
NS
X.25 PSTN LAPB
IEEE 802.2 LLC/SNAP
IEEE802.2 LLC/SNAP
BSSGP
PPP
IEEE 802.3 Ethernet
IEEE802.11 MAC
HDLC
PPP
SLIP
ARCnet
Bluetooth LMP, L2CAP, Baseband
RFCOMM
ATM
FDDI


IEEE 802.5 Token Ring


Hardware Layer
Physical Layer
30
Data-link Layer Processing
Layer 3
Network Layer
Datagram
Data Link Layer
data
Data-link Headers Stripped
Data-Link Headers Appended to Data Field
Layer 2
11011010110111011101110111000110011100000110010100
0111
DataLink Frame
Start of frame source addrdest
addradmindata error chkend of frame
11101110001101
Layer 1
Physical Layer
31
OSI Layer 3 Network Layer
32
Network Layer Processing
33
OSI Layer 4 Transport Layer
34
Transport Layer Processing
35
OSI Layer 5 Session Layer
Application Software Layer
WAP Stack
TCP/IP Stack

WSP

NFS
DNS

36
Session Layer Processing
Layer 6
Presentation Layer
Message
Session Layer
data
Layer 5
Session Headers Stripped
Session Header Appended to Data Field
1101101100110111000110000110
L2CAP Packet
LengthDestination Channel IDData
Message/Packet
Layer 4
Transport Layer
37
OSI Layer 6 Presentation Layer
38
Presentation Layer Processing
Layer 7
Application Layer
Message
Presentation Layer
data
Message conversion
Layer 6
Presentation Header Appended to Data Field
1101101100110111000110000110
Bluetooth Message
LengthDestination Channel IDData
Message
Layer 5
Session Layer
39
OSI Layer 7 Application Layer
40
Embedded Hardware
Stanford University - EE109
41
Many Many Many Embedded Processors To Choose From
42
ISA Models

• Application Specific
• Controller
• Datapath
• Finite State Machine with Datapath FSMD
• Java Virtual Machine
• .
• General Purpose
• Complex Instruction Set Computing CISC
• Reduced Instruction Set Computing RISC
• Instruction Level Parallelism
• Single Instruction Multiple Data SIMD
• Superscaler Machine
• Very Long Instruction Word (VLIW) Computing
• .

43
Implementing an ISA Von-Neumann
44
Embedded Software
Stanford University - EE109
45
Embedded Software The System Software Layer
Application Software Layer
Application Software Layer
System Software Layer
System Software Layer
Application Software Layer
System Software Layer
Operating System Layer
Middleware Layer
Operating System Layer
Board Support Package Layer
Operating System Layer
Device Driver Layer
Device Drivers
Device Driver Layer
Hardware Layer
Hardware Layer
Hardware Layer
Application Software Layer
Application Software Layer
Application Software Layer
Application Software Layer
System Software Layer
System Software Layer
System Software Layer
System Software Layer
Operating System Layer
Middleware Layer

Middleware
Operating System Layer
Operating System Layer
Operating System Layer
Middleware
Middleware
Board Support Package Layer
Board Support Package Layer
Device Drivers
Device Drivers
Device Drivers
Device Driver Layer
Hardware Layer
Hardware Layer
Hardware Layer
Hardware Layer
46
What are Device Drivers?
Application Software Layer
System Software Layer
Device Driver Layer r
Higher-layer Interface ----------------------- Har
dware Interface
Hardware Layer
47
Most Common Types of Device Drivers Routines

• Hardware Startup, initialization of the hardware
  upon power-on or reset.
• Hardware Shutdown, configuring hardware into its
  power-off state.
• Hardware Disable, allowing other software to
  disable hardware on-the-fly.
• Hardware Enable, allowing other software to
  enable hardware on-the-fly.
• Hardware Acquire, allowing other software gain
  singular (locking) access to hardware.
• Hardware Release, allowing other software to free
  (unlock) hardware.
• Hardware Read, allowing other software to read
  data from hardware
• Hardware Write, allowing other software to write
  data to hardware
• Hardware Install, allowing other software to
  install new hardware on-the-fly
• Hardware Uninstall, allowing other software to
  remove installed hardware on-the-fly

48
Embedded Operating Systems

• Process Management.
• Process Implementation
• Scheduling
• Intertask Communication Synchronization
• Interrupt Handling, Error Detection,
• Memory Management.
• Segmentation
• Paging
• Virtual Memory
• System Security
• I/O System Management.
• File System

49
OS Models
Higher-level Software (Middleware, Applications)
Microkernel
Memory Management
Process Management
Device Drivers
I/O
Memory
Interrupt
Hardware
50
Process Management

• What is a process?
• Tasks vs. Threads

51
Unitasking vs. Multitasking OSes
Unitasking OS
Task Program 1 Task Registers Task Stack
Program 1
52
The OS Multitasking Illusion
OS

• How?
• Implementation
• Scheduling
• Synchronization
• Inter-task Communication

53
Process Implementation the Task Hierarchy

• Task Creation
• Task Deletion
• Task Suspension
• Task Resumption

54
Task Creation and Fork/Exec
55
Task Creation Spawn
ltlt Task creation based upon spawn involve 2
major steps gtgt
Memory
Process Table
Parent Task TCB
TCB
TCB
1. Parent task makes spawn system call to create
child task
Spawn System Call
Memory
Process Table
Child Task TCB
TCB
TCB
2. Child Task loaded into memory, including
program, TBC, stack, etc.
56
Task Deletion

• System Call
• Garbage Collection

57
Resuming Suspending Tasks Task States

• 3 Main States
• Ready The process is ready to be executed at
  anytime, but is waiting for permission to use the
  CPU.
• Running The process has been given permission
  to use the CPU, and can execute.
• Blocked or Waiting The process is waiting for
  some external event to occur before it can be
  ready to run.
• Task States and Queues

58
Process State Transition Models

• When a task that is moved from one of the queues
  (READY or BLOCKED/WAITING) into the RUNNING
  state, it is called a context switch.

59
Scheduling in OSes

• Non-preemptive Schedulers
• First-Come-First-Serve (FCFS)/ Run-To-Completion
• Shortest Process Next SPN/ Run-To-Completion
• Co-operative

60
Scheduling in OSes Continued

• Preemptive Schedulers
• Round Robin/FIFO (First-in-First out) Scheduling

61
Scheduling in OSes Continued

• Preemptive Schedulers Continued
• Priority Preemptive Scheduling

62
Scheduling in OSes Continued

• Preemptive Schedulers Continued
• EDF (Earliest Deadline First)/Clock Driven
  Scheduling
• What is an RTOS?
• A preemptable kernel!
• Deterministic

63
Intertask Communication Synchronization

• Memory Sharing
• Message Passing
• Signaling
• Interrupt Handling

64
Memory Management

• User vs. Kernel Memory Space
• User Memory Space Divided Into Partitions
• Segments
• Pages
• What is Virtual Memory?
• User Memory Allocation and Deallocation Scheme
  Depends on Programming Language

65
What is a BSP Board Support Package ?
66
Middleware Application Software
67
Middleware Examples
Application Layer
Middleware Layer
pJava 1.1.8 JVM
java.net Socket API
TCP
UDP
IP
Hardware Layer
68
Application Layer Examples
69
Putting It All Together
Stanford University - EE109
70
6 Stages Creating An Embedded Systems
Architecture

• Stage 1 Having a solid technical base Software
  Hardware
• Stage 2 Understanding the ABCs of Embedded
  Systems
• Stage 3 Defining the architectural patterns
  reference models
• Stage 4 Creating the architectural structures
• Stage 5 Documenting the architecture
• Stage 6 Analyzing and evaluating the
  architecture.

71
Stage 2 Understanding the ABCs Architecture
Business Cycles of Embedded Systems
72
What are General ABC Requirements?

• - Business (Sales Marketing) sellability
  (how the device will sell), time-to-market (when
  will the device be delivered), costs
  (development, overhead, etc.), device lifetime
  (how long the device will be available on the
  market), target market (what type of device it
  is), schedule features (schedule of versions to
  be released with associated features), etc.
• - Technical performance, user friendliness
  (usability), modifiability (how simple it is to
  modify the various functional elements),
  security, reliability, portability, testability,
  availability, technical industry standards (see
  industry standards below), etc.
•  
• - Industry typically are a result of industry
  standards (introduced at start of presentation),
  which may be market specific (i.e. TV standards,
  medical device standards, etc.) or general
  purpose across different families of devices
  (programming language standards, networking
  standards, etc.)
•  
• - Quality Assurance testability (how easily the
  system can be tested), availability (when the
  system is available for testing), schedule
  features (schedule of versions to be tested with
  associated features), QA industry standards (ie
  ISO9000, ISO9001, and so on see industry
  requirements above), etc.
• .

73
Performance Scenerio
System Response Measures (throughput, latency,
data loss, etc.)
Environment (normal, high network
traffic, etc.)
Internal Stimulus Sources (other internal system
elements)
Effected Element (Entire Embedded System)
Performance Stimuli (periodic events, one-time
events, etc.)
System Response (events processed in timely
manner, etc)
External Stimulus Sources (user, data over
network, etc.)
74
How to Derive System Components from Performance
Requirements?
75
Security Scenerio
System Response Measures (latency in system
recovery, effectiveness of system fix for
previously encountered stimuli,etc.)
Environment (normal,
connected/disconnected to network, data uploads/
downloads, etc.)
Effected Element (Data in Memory of Embedded
System, other accessible system services)
External Stimulus Sources (user, data over
network, etc.)
Security Stimuli (system shutdown, altering data,
copying data, etc.)
System Response (recovering, detecting, resisting
attacks, etc)
76
How to Derive System Components from Security
Requirements?
System Response Measures (latency in system
recovery, effectiveness of system fix for
previously encountered stimuli,etc.)
fewer security breeches
Embedded System
External Stimulus Sources (user, data over
network, etc.)
Security Stimuli (system shutdown, altering data,
copying data, etc.)
System Response (recovering, detecting, resisting
attacks, etc)
77
Testability Scenerio
System Response Measures (testing times, number
of tests performed, accuracy of tests, etc.)
Environment (development, production,
in field, etc.)
Internal Stimulus Sources (other internal system
elements)
Effected Element (Some or all software/hardware
elements within Embedded System)
Testability Stimuli (hardware/software completed,
hardware/software update, etc.)
System Response (easily controlled and observable
responses to tests, , etc)
External Stimulus Sources (user, data over
network, etc.)
78
How to Derive System Components from Testability
Requirements?
System Response Measures (testing times, number
of tests performed, accuracy of tests, etc.)
easier testing
Embedded System
Internal Stimulus Sources (other internal system
elements)
Testability Stimuli (hardware/software completed,
hardware/software update, etc.)
System Response (easily controlled and observable
responses to tests, , etc)
External Stimulus Sources (user, data over
network, etc.)
79
Stage 3 Defining the Architectural Patterns
Reference Models
 

• Create the system profile
• Make a matrix to determine if components meet
  cost, time-to-market, performance ... requirements

 
80
Selecting a Programming Language
 
 
81
Selecting an OS
 

• Questions to ask  
• 1.  What type of systems typically use or require
  an OS?
• 2.  Is an OS needed to fulfill system
  requirements?
• 3. What is needed to support an OS in a design?
• 4. How to select the OS that best fits the
  requirements?

 
82
Selecting a Master Processor

• Select processor on requirements and its impact
  on the remainder of the system (especially
  software).
• Why ?
• The master processor essentially impacts what
  enhancements are implementable in software, and
  what constraints are placed upon the software

 
83
Stage 4 Define the Architectural Structures
84
Stage 5 Document the Architecture

• Step 1 A document outlining the entire
  architecture.
• Step 2 A document for each structure.
• Step 3 An architecture glossary.

Rough/Informal Sequence Diagram
UML Sequence Diagram
UML Use Case Diagram
85
Stage 6 Analyze and Evaluate Architecture

• Step 1- Members of the evaluation team obtain
  copies of the architecture documentation from
  the responsible architect (s), and it explained
  to the various team members the evaluation
  process, as well as, the architecture information
  within the documentation to be evaluated.
• Step 2 - A list of the architectural approaches
  and patterns is compiled based upon feedback
  from the members of the evaluation team after
  they have analyzed the documentation.
• Step 3 The architect (s) and evaluation team
  members agree upon the exact scenarios derived
  from the requirements of the system (the team
  responding with their own inputs of the
  architects scenarios changes, additions,
  deletions, etc.), as well as, the priorities of
  the various scenarios are agreed upon in terms of
  both importance and difficulty of
  implementation.
•  
• Step 4 - The (agreed upon) more difficult and
  more important scenarios are where the
  evaluation team spends the most time on
  evaluating, because these scenarios introduce
  the greatest risks.
• Step 5 Results of evaluation team should
  include (at the very least) the 1) uniformly
  agreed upon list of requirements/scenarios, 2)
  benefits (i.e. the ROI Return-On-Investment
  aka. the ratio of benefit to cost), 3) risks, 4)
  strengths, 5) problems, and 6) any of the
  recommended changes to the evaluated
  architectural design.