3D Circuit Integration Technology for Multiproject Fabrication

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3D Circuit Integration Technology for
Multiproject Fabrication
Program Kickoff 7 April 2000 L-325, MIT Lincoln
Laboratory
Break and Camera Demonstration
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3D Circuit Integration Technology for
Multiproject Fabrication
TREX Enterprises System Integration New Research
in 3D Architectures and Systems
Summary of Prior Results
Lisa McIlrath 840-900
Lisa McIlrath 900-930
New Program Overview
Steve Hawley 930-950
High Resolution Camera Design
Algorithms for Activity Detection with 3D Sensors
Victor Lum 950-1005
Break and Camera Demonstration
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N1 Test Reticle Layout
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N1 3D Photodiode Active Pixel

• 10mm via
• 32mm x 37mm
• pixel area

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3D Transfer/Via SEMs - 9/98
Deep and shallow 10mm vias - top view
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N1 Via Chain Measurements - 9/98
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N1 Diode Measurements - 9/98
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N2 Test Reticle Layout
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6 mm via on 150mm wafer -- 7/23/99
Aluminum
Oxide
Adhesive
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Photomicrograph of Imager
Metal-1 Pad
3D Via
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N2 2D 3D Ring Oscillator Measurements
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First 3D 64x64 Imager Results - 9/99
Dark Image
Room Light
Bright Light
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NU - LL 3D Technology Transfer

• Wafer-to-wafer bonding process under development
  at Lincoln Laboratory
• Traveller of NU 3D process delivered to Lincoln
• Complete devices from North 3 and 4 runs
• Transfer Keith Warner to Lincoln - (task
  completed)

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3D Pixel Design Free-Running Sampled Oscillator
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3D 2D Pixel Layouts
MOSIS HP 0.5mm process 30mm x 30mm pixel
3D SOI-CMOS 0.8mm process 2-layer 45mm x 45mm
pixel
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Circuits / Systems Design Status
Pixel-Parallel A/D Imager Design -- Tests /
Design Revs Complete
40nW / pixel _at_ 3.3V, 0.1 Residual Fixed
Pattern Noise
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Circuits / Systems Design Status
3rd Layer Design Taped Out 11/1/99

• On-chip VCO with 216 (65536) bit range
• On-chip pixel-parallel 1st stage low pass
  filtering
• Programmable resolution / dynamic range

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Circuits / Systems Design
Systems Environment

• Camera demo system modified for 256 x 256 imager
  compatibility and interface upgrade
• Research in future smart sensor designs
• Video tracking demo (V. Lum, M-Eng thesis)
• Video feedback control architectures (A. Aina,
  PhD thesis)

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Testbed DemonstrationCamera System
(Demo Setup in Office)
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Activity Monitoring
Current image
Background model
Detected objects
Object Tracking Using Adaptive Background Mixture
Models Courtesy Chris Stauffer Eric Grimson
MIT Artificial Intelligence Laboratory
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Analog Memory with Digital Feedback
Change detector
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Multimode memory module
Pixel Input
active
F.D.
Monitor
enable
VCO
Charge Pump
active
F.D.
Monitor
enable
VCO
Charge Pump
Problem VCO tracks new values faster than
monitor detects them
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Compensated Memory
Solution Integrate a low pass filter into the
loop
active
Pixel Input
F.D.
Filter
enable
VCO
Charge Pump
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Creating the Filter
Edge Counter
active
reset
enable
Compare Logic
Edge Counter
reset
Pixel Input
F.D.
Edge Counter
reset
VCO
Charge Pump
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Detecting Activity
Activity is determined by the temporal distance
between pairs of unmatched edges
Second unmatched edge
Pixel Bitstream
VCO output
Input frequency change
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The Enabling Technology

• Better circuit / interconnect ratio
• Unrestricted vertical interconnections between
  layers
• Low digital system power PCV2f

SOI CMOS
3D
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Path to Industrialization
Goals

• Industry-Standard State-of-the-Art SOI/CMOS
  Process
• Automated Wafer Align / Bonding / Interconnect
  Patterning

• Phase I Infrastructure Development
• Phase II Small Volume 3D Processing Center for
  Multi-Project Runs
• Phase III High Volume Manufacturing

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Phase I Plan (25 months)

• Process Development
• 0.8mm SOI/CMOS 0.18, 0.25 mm FDSOI
• Reliable low temperature oxide bonding
• High aspect ratio Tungsten plug fill
• Systems Development
• High Definition Imager Platform
• 3D-compatible near-IR imaging technique
• 3D CAD tools packaging

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Systems Design Schedule
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0.25mm FDSOI Test Pixel
14mm x 14mm (or less)
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High-Resolution Near-IR Imager

• Explore best method for III-V incorporation with
  automated 3D process technology
• Proposal accepted from C. Fonstad, MIT, for
  selective InGaAs in Si growth
• Initial photodiode array lots for investigation
• Imager design unchanged
• Compatible with basic platform systems demo

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3D CAD Tools

• Develop minimal toolset for 3D cell layout,
  design rule checking, netlist extraction
• Interface with commonly available tools, e.g.,
  Magic, L-Edit, Spice
• Platform independent
• Remove major obstacle for new users in Phase II
• Plan
• Build on prior work developed on Cadence tools
• Negotiate distribution agreement with Si-valley
  software vendor(s).

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High Definition Imager Platform

• Interface 3D camera with SXGA (1024x1280) display
• Identify military users
• Human factors issues