SEQUENTIAL CIRCUITS

1
SEQUENTIAL CIRCUITS

• DEFINITION OF SEQUENTIAL CIRCUIT
• SYNCHRONOUS SEQUENTIAL CIRCUIT
• ASYNCHRONOUS SEQUENTIAL CIRCUIT
• MEMORY ELEMENTS
• CLASSIFICATION LATCHES AND FLIP-FLOPS
• LATCHES
• BASIC LATCH
• GATED LATCH
• EFFECT OF PROPAGATION DELAYS
• FLIP-FLOPS
• ASYNCHRONOUS SEQUENTIAL CIRCUIT
• ASYNCHRONOUS BEHAVIOR
• ANALYSIS OF ASYNCHROUNOUS CIRCUITS

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof. Marin.
Revised 2005-02-14. Figures taken from
Fundamentals of Digital Logic with VHDL Design,
S. Brown and Z. Vranesic, 2nd Edition, McGraw
Hill.
2
DEFINITION OF SEQUENTIAL CIRCUIT

• CIRCUITS IN WHICH THE VALUES OF THE OUTPUTS
  DEPENT ON
• THE PRESENT VALUES OF THE INPUTS
• THE PAST BEHAVIOR OF THE CIRCUIT
• ARE CALLED SEQUENTIAL CIRCUIT.
• IN SUCH CIRCUITS STORAGE ELEMENTS STORE
• THE VALUES OF THE SIGNALS. THE CONTENTS OF THE
• STORAGE ELEMENTS REPRESENT THE STATE OF THE
• CIRCUIT.
• THERE ARE TWO TYPES
• SYNCHRONOUS, AND
• ASYNCHRONOUS

3
DEFINITION OF SEQUENTIAL CIRCUIT

• SYNCHRONOUS SEQUENTIAL CIRCUITS
• ARE SEQUENTIAL CIRCUITS CONTROLLED BY A CLOCK
  SIGNAL

4
DEFINITION OF SEQUENTIAL CIRCUIT

• ASYNCHRONOUS SEQUENTIAL CIRCUITS
• ARE SEQUENTIAL CIRCUITS
• WITH NO CLOCK SIGNALS,
• NO FLIP-FLOPS TO STORE STATE VARIABLES
• Feedback signal Gate-delay

5
MEMORY ELEMENTS

• EXAMPLES OF MEMORY ELEMENTS

6
MEMORY ELEMENTS

• CLASSIFICATION LATCHES AND FLIP-FLOPS
• BASIC LATCH is a feedback connection of two NOR
  gates or two NAND gates.
• GATED LATCH is a basic latch that includes input
  gating and a
  control input signal.
• FLIP-FLOPS is a storage element based on the
  gated latch principle which can
  have its output state
  changed only at the edge of the
  controlling clock signal.

7
MEMORY ELEMENTS

• CLASSIFICATION LATCHES AND FLIP-FLOPS
  (Continues)
• The state of the LATCH keeps changing according
  to the values of the input signals during the
  period when the clock is active.
• The state of the FLIP-FLOP changes only at the
  edge of the controlling clock signal.

8
MEMORY ELEMENTS

• LATCHES BASIC LATCH

9
MEMORY ELEMENTS

• LATCHES GATED RS LATCH

10
MEMORY ELEMENTS

• LATCHES GATED D LATCH

11
MEMORY ELEMENTS

• EFFECT OF PROPAGATION DELAYS Latch Setup and
  hold times.
• SETUP TIME Minimum time that the D input signal
  must be stable prior to the negative (positive)
  edge of the Clk (clock) signal.
• HOLD TIME Minimum time that the D input signal
  must remain stable after the negative (positive)
  edge of the Clk (clock) signal

12
MEMORY ELEMENTS

• FLIP-FLOPSThey are storage elements that
  can change their state no more than
• once during one clock cycle. Two types
  Master-Slave and Edge-triggered.
• Master-Slave Flip-flop

13
MEMORY ELEMENTS

• FLIP-FLOPS (Continues).
• Edge-triggered Flip-flop

14
MEMORY ELEMENTS

• INPUT/OUTPUT BEHAVIOR OF LATCHES AND FLIP-FLOPS

TYPES WHEN INPUTS ARE SAMPLED WHEN OUTPUTS ARE VALID
UNCLOCKED LATCH (Basic latch) ALWAYS PROPAGATION DELAY FROM INPUT CHANGE
LEVEL-SESITIVE LATCH (Gated latch) CLOCK HIGH tsu , th around falling clock edge PROPAGATION DELAY FROM INPUT CHANGE
POSITIVE-EDGE FLIP-FLOP CLOCK LOW-TO-HIGH TRANSITION tsu , th around rising clock edge PROPAGATION DELAY FROM RISING EDGE OF CLOCK
NEGATIVE-EDGE FLIP-FLOP CLOCK HIGH-TO-LOW TRANSITION tsu , th around falling clock edge PROPAGATION DELAY FROM FALLING EDGE OF CLOCK
MASTER-SLAVE FLIP-FLOP CLOCK HIGH-TO-LOW TRANSITION tsu , th around falling clock edge PROPAGATION DELAY FROM FALLING EDGE OF CLOCK
_______________________________________
Contemporary Logic Design by R.H. Katz, Benjamin
Cummings, 1994, page 290.
15
MEMORY ELEMENTS

• LEVEL-SENSITIVE VERSUS EDGE-TRIGGERED STORAGE
  ELEMENTS

(a) Circuit
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MEMORY ELEMENTS

• FLIP-FLOPS (Continues)
• CHARACTERISTIC AND EXCITATION EQUATIONS OF
  D, T AND J-K FLIP-FLOPS

Type Symbol Characteristic Excitation
D-type D Q 0 0 1 1 Q Q D 0 0 0 0 1 1 1 0 0 1 1 1
T-type T Q 0 Q 1 !Q Q Q T 0 0 0 0 1 1 1 0 1 1 1 0
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MEMORY ELEMENTS
FLIP-FLOPS (Continues) CHARACTERISTIC
AND EXCITATION EQUATIONS OF D, T AND J-K
FLIP-FLOPS
Type Symbol Characteristic Excitation
J-K-type J K Q 0 0 Q 0 1 0 1 0 1 1 1 !Q Q Q J K 0 0 0 x 0 1 1 x 1 0 x 1 1 1 x 0
SR-type (not in use shown here for completeness) S R Q 0 0 Q 0 1 0 1 0 1 1 1 Forbidden Q Q S R 0 0 0 x 0 1 1 0 1 0 0 1 1 1 x 0
Q
J
K
!Q
Clk
gt
S
Q
R
!Q
Clk
gt
18
MEMORY ELEMENTS

• FLIP-FLOPS (Continues)
• FLIP-FLOP CONVERSIONS Given a flip-flop as a
  buiding block, produce another type of flip-flop.
• APPROACH Determine the input logic to the given
  flip-flop by satisfying the condition that both
  flip-flops must have identical logic behavior
  (their outputs are the same)

19
MEMORY ELEMENTS

• FLIP-FLOP CONVERSIONS (Continues)
• Example Produce the circuit of a J-K-type
  flip-flop using a T-type flip-flop as a building
  block and NAND gates as needed
• The corresponding circuit is shown on next slide

J K Q QJK QT T
0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1
T J !Q K Q
20
MEMORY ELEMENTS

• FLIP-FLOP CONVERSIONS
• Example (Continues) Circuit of a J-K flip-flop
  using a T flip-flop

21
ASYNCHRONOUS SEQUENTIAL CIRCUIT

• IN SYNCHRONOUS SEQUENTIAL CIRCUITS A CLOCK SIGNAL
  CONSISTING OF PULSES, CONTROLS THE STATE
  VARIABLES WHICH ARE REPRESENTED BY FLIP-FLOPS.
  THEY ARE SAID TO OPERATE IN PULSE MODE.
• IN ASYNCHRONOUS CIRCUITS STATE CHANGES ARE NOT
  TRIGGERED BY CLOCK PULSES. THEY DEPEND ON THE
  VALUES OF THE INPUT AND FEEDBACK VARIABLES.
• TWO CONDITIONS FOR PROPER OPERATION
• 1.-INPUTS TO THE CIRCUIT MUST CHANGE ONE AT A
  TIME AND MUST
• REMAIN CONSTANT UNTIL THE CIRCUIT
  REACHES STABLE STATE.
• 2.-FEEDBACK VARIABLES SHOULD CHANGE ALSO ONE AT
  A TIME. WHEN
• ALL INTERNAL SIGNALS STOP CHANGING, THEN THE
  CIRCUIT IS
• SAID TO HAVE REACHED STABLE STATE.
• WHEN THE INPUTS SATISFY CONDITION 1 ABOVE, THEN
  THE CIRCUIT IS
• SAID TO OPERATE IN FUNDAMENTAL MODE.

22
ASYNCHRONOUS SEQUENTIAL CIRCUIT

• ASYNCHRONOUS BEHAVIOR
• Consider the Set-Reset latch.
• The gates shown below have no delay. Their delay
  (twice one-gate delay) is represented by the
  square.

23
ASYNCHRONOUS SEQUENTIAL CIRCUIT

• ASYNCHRONOUS BEHAVIOR Set-Reset latch
  (continues)
• The circuit behavior is represented by a
  State-assigned table or Flow table which show
  every possible transition of the circuit for each
  input value. Stable-states are those circled in
  the table because, while the inputs are stable,
  present state is equal to next state (internal
  variables stop changing). Columns with no circled
  sates indicate circuit oscillation for that
  particular input value.

24
ASYNCHRONOUS SEQUENTIAL CIRCUIT

• ASYNCHRONOUS BEHAVIOR Set-Reset latch
  (continues)
• FINITE-STATE-MACHINE MODEL MOORE MODEL

25
ASYNCHRONOUS SEQUENTIAL CIRCUIT

• ASYNCHRONOUS BEHAVIOR Set-Reset latch
  (continues)
• FINITE-STATE-MACHINE MODEL MEALY MODEL
• (a) State Table
• (b) State Diagram

26
ASYNCHRONOUS SEQUENTIAL CIRCUIT

• ANALYSIS OF ASYNCHROUNOUS CIRCUITS
• PROCEDURE
• CUT ALL FEEDBACK PATHS AND INSERT A DELAY ELEMENT
  AT EACH POINT WHERE CUT WAS MADE
• INPUT TO THE DELAY ELEMENT IS THE NEXT STATE
  VARIABLE Yi WHILE THE OUTPUT IS THE PRESENT
  VALUE yi.
• DERIVE THE NEXT-SATE AND OUTPUT EXPRESSIONS FROM
  THE CIRCUIT
• DERIVE THE EXCITATION TABLE
• DERIVE THE FLOW TABLE
• DERIVE A STATE-DIAGRAM FROM THE FLOW TABLE

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ASYNCHRONOUS SEQUENTIAL CIRCUIT

• ANALYSIS OF ASYNCHROUNOUS CIRCUITS EXAMPLE

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ASYNCHRONOUS SEQUENTIAL CIRCUIT

• ANALYSIS OF ASYNCHROUNOUS CIRCUITS EXAMPLE
  CONTINUES

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ASYNCHRONOUS SEQUENTIAL CIRCUIT

• SYNTHESIS OF ASYNCHROUNOUS CIRCUITS
• THIS TOPIC IS NOT COVERED IN THIS COURSE. IT
  BELONGS TO A MORE ADVANCED LOGIC DESIGN COURSE.
• THIS SUBJECT IS VERY IMPORTANT IN TODAYS DIGITAL
  SYSTEMS DESIGN BECAUSE CLOCKS ARE SO FAST THAT
  THEY PRESENT PROPAGATION DELAYS MAKING SUBSYSTEMS
  TO OPERATE OUT OF SYNCHRONIZATION.
• TECHNIQUES FOR SYNTHESIS OF ASYNCHRONOUS CIRCUITS
  INCLUDE
• THE HOFFMAN OR CLASSIC SYNTHESIS APPROACH
• HANDSHAKING SIGNALING FOR TWO SUBSYSTEMS TO
  COMMUNICATE ASYNCHRONOUSLY