5. Sequential functions and circuits

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Lecture 5

• 5. Sequential functions and circuits
• 5.1 Introduction
• 5.2 Feedback, memory, state
• 5.3 Sequential functions and circuits
• 5.4 Flip-flops
• 5.5 The S-R flip-flop
• 5.6 Examples

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5.1 Introduction

• In the preceding chapters we have discussed
  various types and aspects of combinational
  functions, whose outputs are determined
  completely by their inputs.
• An important property ot that functions and
  circuits, where these functions are implemented,
  is that there is no feedback from the output to
  the input

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5.2 Feedback, memory, state

• The moment we introduce this feedback, we get a
  new type of function or circuit with a new
  capability
• -The capability to store bits of information.
• In other words the circuit also acquires memory.
• Depending on the contents of its memory,
• we say that the circuit is in a certain state

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Feedback, memory, state - 2

• Therefore a change in the contents of the memory
  implies a change in the state of the circuit.
• The output of such a circuit with memory is not
  always the same for the same input, as is the
  case with a combinational circuit but also
  depends on its present state.

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Feedback, memory, state - 3

• Note, that we have used the word present in the
  last sentence.
• This means that the next state as well as the
  output depend not only on the present input but
  also the present state.
• Hence the element of time also comes in.
• Such combinational functions (circuits) with
  feedback , having memory of internal states, are
  called sequental functions (circuits).

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5.3 Sequential functions and circuits

• Such combinational functions (circuits) with
  feedback , having memory of internal states, are
  called sequental functions (circuits).
• A formal definition of sequential circuits or the
  more general term sequential machines
  (automatons) will be given later.

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Sequential functions and circuits -1

• There are three special types of sequential
  machines
• Flip-flops
• Counters
• Shift registers
• The building blocks of all these sequential
  circuits are the flip-flops, which we discuss
• in this lecture.

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5.4 Flip-flops

• A flip-flop is the most elementary sequential
  machine having only two states.
• These are therefore bistable circuits.
• Although the flip-flops may differ in their
  electronic compositions, they exhibit certain
  definite logical properties.

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Flip-flops - 2

• In fact, all flip-flops, irrespective of their
  internal circuit implementation, can be
  classsified into a few types according to their
  logical behavior.
• The R-S flip-flop
• The J-K flip-flop
• The D flip-flop
• The T flip-flop

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Flip-flops - 3

• In subsequent sections we first discuss a few
  typical types of flip-flops and then we seehow
  theese flip-flops produce various types of
  conters and shift registers depending on their
  interconnections

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Flip-flops - 4

• In PLC we usually have some of these flip-flops
  at disposal (mostly RS flip -flop and /or SR
  flip-flop) as co called function blocks (SW
  function blocks).
• We only program these blocks, that means we
  connect them with other blocks in one of the
  programming languages for PLCs named Function
  block diagram - FBD (see e.g. LOGO! )

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5.5 The S-R flip-flop

• Consider the circuit shown in the figure

Z1
S
gt1 G1
NQ
gt1 G2
Q
R
Z2
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The S-R flip-flop - 2

• It is a combinational circuit with feedback

Z1
S
gt1 G1
It has only two NOR gates,G1 and G2, with the
output of one gate being fed to the input of the
other
NQ
gt1 G2
Q
R
Z2
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The S-R flip-flop - 3

• Now let us study the outputs of the circuit Z1
  and Z2 for the four different combinations
  00,01,10,11 of the input lines S and R.
• 1.When S0, Z1 becomes 1(0) depending on if
  Z20(1)
• Z1N(SZ2)NS.NZ21.NZ2NZ2
• Z11.1.Z20
• Z11.0.Z21

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The S-R flip-flop - 4

• 2. Similarly, when R0, Z2NZ1, since
• Z2N(RZ1)NR.NZ11.NZ1NZ1
• 3. Thus when SR00, the values of Z1and Z2 depend
  only on them and it is always
• Z1NZ2.
• It can now be verified, that with SR00, if
  Z1Z201 or Z1Z210, they retain these output
  values.
• In other words, the outputs remain unchanged.

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The S-R flip-flop - 5

• 4.However the situation changes if S1 and R0,
  then the 1 on the S-line will force the output Z1
  to be 0, irrespective of the value of Z2.
  Therefore Z1 becomes 0. This forces Z2 to become
  1, as both input lines of gate G2 become 0.
• Hence when SR10, the circuit has a stable state
  with Z1Z201.

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The S-R flip-flop - 6

• 5. Similarly it can be found, that the circuit
  has another stable state with SR01 and Z1Z2
  becoming 10.
• 6. Now, let us investigate what happens, if
  SR11. In this situation, the 1 on the S-line
  will force Z1 to be 0, and the 1 on the R-line
  will force Z2 to be 0. So under this conditions,
  when SR11, the output will be Z1Z200 and this
  will also be a stable state.

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The S-R flip-flop - 7

• 7. Now, let S and R both become 00 simultanously.
  Then both NOR gates, G1 and G2, will see 00 at
  their inputs simultaneously, and their outputs
  will tend to become 11. Now let the output Z1 of
  gate G1 change to 1much earlier than Z2 of gate
  G2. Then the 1 at Z1 will prevent Z2 to become 1
  and Z2 will continue to remain 0. Now it can be
  easily checked that the output Z1Z210 with SR00
  is also a stable state.

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The S-R flip-flop - 8

• 8. However, when S and R become 00
  simultaneously, if Z2 would have become 1 much
  earlier than Z1, the output will stabilize at the
  value of Z1Z201. Thus the outputs become
  unpredictable and depend on the operating delays
  of the gates G1 and G2.

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The S-R flip-flop - 9

• Even if these two delays are identical, there is
  a serious problem.
• In that case it can beverified that the outputs
  will oscillate between the values 11 and 00.
• These are very undesirable operating conditions
  for the flip-flop.

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The S-R flip-flop - 10

• Thus although SR11 and Z1Z20 is a stable state,
  it may introduce serious anomalous situations in
  operation of the flip-flop.
• Hence to eliminate this possibility entirely, an
  aditional restriction, that the S- and R-lines
  should not be made 1 simultanously, is accepted
  in the definition of an S-R flip-flop.

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S-R flip-flop - 11

• Definition
• An S-R flip-flop has two input lines, S and R.
  When S is 1, the flip flop is set to state 1.
  When R becomes 1, the flip flop is reset to
  state 0. When both S and R are 0, the flip-flop
  continues to be in the same state. The S- and
  R-lines are never made 1 simultaneously. When
  the flip-flop is in state 0(1), the output of the
  flip-flop Q is also 0(1).

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S-R flip-flop - 12

• This definition yields the truth table,(next
  snap), where q denotes the present state and Q
  the next state of the flip-flop.
• The truth table defines Q as a function of the
  three variables S, R, and q
• Qf(S,R,q)

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S-R flip-flop - 13

• The truth table of S-R- flip-flop

As a sum of minterms it can be expressed
as Q(S,R,q)SUM(1,4,5) x
SUM(6,7) NS.NR.qS.NR.NqS.NR.q ???(assume,
that x1).. S.R.nqS.R.qSNR.q

• S R q Q
• 0 0 0 0
• 0 0 1 1
• 0 1 0 0
• 0 1 1 0
• 0 0 1
• 1 0 1 1
• 1 0 x
• 1 1 1 x

This function is known as the characteristic
function of the RS flip-flop.
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The S-R flip-flop 14

• Theory says all this .but what about praxis???
• In practical applications, we must solve the
  situation when S1 and R1 simultaneously
• There are two types of SR flip-flops (both HW and
  SW applications)
• SR - with prior setting
• (if SR11, then Q1)
• RS - with prior reseting
• (if SR11, then Q0)

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The S-R flip-flop - 15

• The truth table of S-R- flip-flop with prior
  setting (x1)

As a sum of minterms it can be expressed
as Q(S,R,q)SUM(1,4,5,6,7) NS.NR.qS.NR.NqS.
NR.q S.R.nqS.R.qNS.NR.q S.(NR.NqNR.qR.NqR
.q) NS.NR.qS(NRR) NS.NR.qSNR.qS SNR.q

• S R q Q
• 0 0 0 0
• 0 0 1 1
• 0 1 0 0
• 0 1 1 0
• 0 0 1
• 1 0 1 1
• 1 0 1
• 1 1 1 1

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The R-S Flip-flop - 16

• The truth table of R-S flip-flop with prior
  resetting (x0)

As a sum of minterms it can be expressed
as Q(S,R,q)SUM(1,4,5) NS.NR.qS.NR.NqS.NR.q
NS.NR.qS.NR NR.(NS.qS) NR.(qS)

• S R q Q
• 0 0 0 0
• 0 0 1 1
• 0 1 0 0
• 0 1 1 0
• 0 0 1
• 1 0 1 1
• 1 0 0
• 1 1 1 0

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The S-R Flip-flops - 17

• Practical summary of the RS-flip-flops function
• RS(SR) flip-flop (RS(SR) memory) has two inputs
• S input for setting the output Q (Q1)
• R input for reseting the output Q (Q0)
• If both R and S inputs are 0, output remains on
  its last value.
• If on both S and R inputs are 1 simultaneously,
  the value of output depends on the type of the
  flip flop (SR Q1,RSQ0)
• Very often the R-S flip-flop blocks have the
  second output, negation of the output Q, NQ.

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The S-R Flip-flop - 18

• Block diagram and function table
• (function table is not the same as the true
  table, it serves for the function description )

• S R Q NQ
• 0 1 0
• 0 0 1 0
• 0 1 0 1
• 0 0 0 1
• 1 1 1 0

S
Q
NQ
SR
R
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The R-S Flip-flop - 19

• Block diagram and function table

• S R Q NQ
• 0 1 0
• 0 0 1 0
• 0 1 0 1
• 0 0 0 1
• 1 1 0 1

S
Q
NQ
RS
R
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5.6 Examples

• Example 1
• If sensor B1 has a 1-signal, this indicates an
  error status in the system. A horn H1 is sounded.
  The horn can only be switched off by actuating
  push button S1. It is possible to switch off the
  horn, even if the B1-signal continues to be
  applied.

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Example 1 - 2

• Block diagram of the system

B1
H1
S1
The control system has two
inputs, from B1,S1 one output to
the H1
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Example 1 - 3

• Lets try to solve the task intuitively
• We use SR flip-flop in the control system first.
• Horn H1 will be connected to the output Q of the
  flip-flop.
• This output should be switched on (set) by error
  status (indicated by the sensor B1) thus we
  connect sensor B1 to the S-input of the
  flip-flop.
• This output should be switched off (reset) by
  push button S1thus we connect push button S1 to
  the R-input of the flip-flop.

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Example 1 - 4

• The first solution

B1
S
Q
H1
SR
S1
R
NQ
The basic function is OK, but the last sentence
of the task definition cannot be fulfilled by
this type of flip-flop. If the B1-signal
continues to be applied, (this is Set signal for
SR flip-flop), it is not possible to reset this
flip-flop by its reset signal S1!
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Example 1 - 5

• Lets try the second type of the flip-flop, the
  RS-one.
• Horn H1 will be connected to the output Q of the
  flip-flop.
• This output should be switched on (set) by error
  status (indicated by the sensor B1) thus we
  connect sensor B1 to the S-input of the
  flip-flop.
• This output should be switched off (reset) by
  push button S1thus we connect push button S1 to
  the R-input of the flip-flop.

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Example 1 - 6

• The second solution

B1
S
Q
H1
RS
S1
R
NQ
The basic function is OK. Also the last sentence
of the task definition is fulfilled by this type
of flip-flop. If the B1-signal continues to be
applied, (this is Set signal for RS flip-flop),
it is possible to reset this flip-flop by its
reset signal S1 and thus switch off the horn.
This solution is the right one.
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Example 2

• Example 2
• Pressing of the start button S2 is to cause the
  piston of a cylinder to advance (if it is in
  initial position, that is retracted) signal
  Y11. This mechanism is to be used to clamp
  workpieces. When the piston has advanced fully,
  it is to remain in this position for 20 seconds.
  (Signal Time_out from the special timer block
  is on).The cylinder then returns to its initial
  position signal Y10. Sensor B1 indicates, that
  cylinder is retracted, sensor B2 indicates, that
  cylinder is advanced.

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Example 2 - 2

• Block diagram of the system

S2
Y1
B1
B2
Time_out
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Example 2 - 3

• We use SR flip-flop in the control system.
• Signal for cylinder Y1 will be connected to the
  output Q of the SR flip-flop.
• This output should be switched on (set) by
  pressing the start button S2 if the piston is in
  retracted position (indicated by the sensor B1)
• thus we connect conjunction of the signals
  S2 and B1 to the S-input of the SR flip-flop.

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Example 2 - 4

• This output should be switched off (reset) when
  the piston has advanced fully (indicated by
  sensor B2) and has remained there for 20 seconds
  (signal from timer Time_out).
• thus we connect conjunction of the signals S2
  and Time_out to the R-input of the SR flip-flop.

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Example 2 - 5
S2

B1
Q
S
Y1
SR
R
NQ
B2

Time_out
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Literature

• Nripendra N. Biswas Logic Design Theory,Prentice
  Hall International,1993,ISBN 0-13-010695-X