Stefanos Skoulaxinos

1
Reliable SW/HW Co-Design for Wireless
Communication System Integrating the Spin Model
Checker and Celoxica's DK Suite
BOF-W Verification of Large Designs and Related
Design Methodologies

• Stefanos Skoulaxinos
• School of EPS School of MACS
• Heriot-Watt University, Edinburgh

MAPLD2005/116
Skoulaxinos
1
2
SW-HW Co-Design a trip from idealism to
realism
Dangers - Irrational Abstraction Raising the
design level at a theoretical and impractical
level for targeted application - Flawed
Synthesis process
Potential - Increased system readability and
testability, fast code turn-arounds, impressive
productivity gains - Bridging the gap between
software and hardware development methods and
tools - Application of high level reliability
enhancement strategies - Level of abstraction
can lift the designer seat enabling more complex
applications through a more testable
development process - Possibility of monitoring
and healing system defects (SW or HW) through a
multi- layered software architecture
(Operating System). Lower levels of fault
tolerance (TMR) can be synthesized by the
Compiler automatically.
MAPLD2005/116
Skoulaxinos
2
3
Application Overview LRID Tag
MAPLD2005/116
Skoulaxinos
3
4
LRID Tag - Main Operation
MAPLD2005/116
Skoulaxinos
4
5
Reliability Enhancement Strategies
1 Fault Prevention __ High Quality
Specification Design Diversity Modeling,
Formal Verification Testing Structured
Design Principles
Applied to the Tag
V
V
V
V
2 Fault Tolerance __ Run Time monitoring
(Watchdog Timers) Fault Location and Isolation
SW/HW Redundancy N-Version Programming, Voting
Schemes
Applied to the Tag
V
V
V
MAPLD2005/116
Skoulaxinos
5
6
Formal Verification of Tag Application
The tag protocol was modelled and formally
verified in the Spin Model Checker. Spin is
considered one of the most efficient software
verification tools currently available. It is
actively used in safety critical NASA
applications such as the application to Cassini
(mission to Saturn) and the Mars Pathfinder.
MAPLD2005/116
Skoulaxinos
6
7
Structured Design Flow
MAPLD2005/116
Skoulaxinos
7
8
Run Time Monitoring
MAPLD2005/116
Skoulaxinos
8
9
FPGA platform utilized
MAPLD2005/116
Skoulaxinos
9
10
Reliability Estimation
Notes Test Results were analysed in the CASRE
Reliability Estimation Tool (developed by
JPL-NASA)
MAPLD2005/116
Skoulaxinos
10
11
Conclusions
11
MAPLD2005/116
Skoulaxinos