Apollo

1
Apollo User Guide
2
0. ?? ? Case Mode? Setting .cshrc? ??
setenv AQUARIUS /cad/Avant/Aquarius.2.2.0.113_SOL
setenv APOLLO /cad/Avant/Apollo.4.3.1.
0.19 setenv XLOCALEDIR APOLLO/etc/locale
setenv LM_LICENSE_FILE APOLLO/licenses/li
cense.dat path (APOLLO/bin
AQUARIUS/bin path) setenv XKEYSYMDB
APOLLO/etc/XKeysymDB alias AP apollo
alias MI Milkyway Apollo? ????? ??
????? ???? ASIC Basic Library? Case Sensitive??
??? Basic Library? Access? Design Library?
Creation?? ??? ???. ???? Case Mode? Setting?
setCaseSensitive t ?? command? ?? working
directory ? ?? command? ?? .avntrc ?? file?
??? program ??? ???? setting ??. 1. Physical
GDS? Synopsys Timing ??? Library? ?? Flow
Create library with MilkywaygtLibrarygtCreate
Technology File
GDS Stream File
Read cell layout with Milkyway gtCell
LibrarygtStream In
Cell Type Definition File
Identify power and ground ports
with dbSetCellPortTypes Milkyway gtCLFgtLoad
Synopsys Library source File (.lib file)
Smash with Milkyway gt Cell Library gtSmash
Synopsys
Extract pins, blockage, and vias with Milkywaygt
Cell Library gtBlockage, Pin, Via
Read library source file with read_lib
UNIX egrep
Apollo??? ???? AquariusBV? ?? ?? ???.
Make library report file with report_lib
Adjust cell boundary and create unit tile
with Milkywaygt Cell Library gtSet PR Boundary
K factor File
Synopsys Library report
Define and check tracks with ApollogtDesign
SetupgtWire TracksgtDefine Unit Tile Wire
Tracks ApollogtDesign SetupgtWire TracksgtCheck Pin
on Track
Translate to CLF with MilkywaygtCLF gtSynopsys To
CLF
Linear Timing Model? Table Look Up Model? ??? ?
??? translate linear model to table look up
option ? ON? ???? ??.
If needed, load timing CLF file
with MilkywaygtCLFgtLoad
Timing CLF File
1
3
2. MCP? PMD? ??? Library? ?? Flow
Create library with MilkywaygtLibrarygtCreate
Compass?case insensitive ??? MCP? PMD File?
??? ???? Netlist? Cell Name? Port Name?
???????.
ApoMaker
P2C
Linear Timing Model? Table Look Up Model? ??? ?
??? translate linear model to table
look upoption ? ON? ???? ??. ?? ??? clf file?
TLU model? ??? ????.
If needed, load timing CLF file
with MilkywaygtCLFgtLoad
(1) P2C? ?? Compass PMD(Primitive Model
Description) Timing File?? Aquarius CLF Timing
File? Translation??? Utility? PMD file??? PMD
List File? Derating Factor File? ????.
Derating File? ??
PMD List File? ??
MIN 0.6 TYP 1.0 MAX 1.5
ASRAM.pmd mdpath.pmd
P2C??? ?

compass V Pmd To Avant!
Clf Translator for Compiled Cell Ver
by Myeong-Jin Kim in DM
Gr.
PMD FILES' PATH
. LIBRARY NAME TEST OUTPUT CLF FILE NAME
test.clf DERATING FACTOR FILE NAME
test.der CELL LIST FILE NAME test.plis gtgt
Translation To a is completed !! ltlt !! Please
Check the Log File(TEST_time.log) !!
4
(2) ApoMaker? ?? Compass MCP (Mega Cell
Phantom) File?? Aquarius Library? ??? ??
Utility. ???? Option? ??? ??. - lambda
MCP file? ??? ???? ??? micron?? ??? ? ????.
- pin MCP file? ??? pin text? ????? Pin?
Rectangle? Cell Boundadry??? ??
??? ???? ?(micron)?? Compass??? default? 1 lambda
?? Pin? ????. - Metal3 Blockage Macro
Block? ?? Routing? Metal1? Metal2? ? ???? Y? ??
- spc pin? blockage ?? ??. metal1,
metal2, metal3 ??? ?? Technology File ??
layerTable section? layout attribute? spacing?
???? ??? 3?? metal ??? ?? ? ??
????????. - Must Join Pin Macro Cell ??
Interface? ??? Pin ??? ?? ?? Pin?? Access ??
?? Macro Cell ???? ?? ???? ??? Y?
??????. P/G pin? ?? Macro cell???? voltage
drop? ??? ?? Y? ????. - Extract for DLM
default? TLM or QLM??? DLM? ??? Y? ???? ??. -
Case Sensitivity default? case sensitive

A M
M A A MM MM
K A A PPPPP OOO M M M M AA K
K EEE R RR A A P P O O M M
M A A K K E E R R AAAAAA P P
O O M M A A KKK EEEEEE RR A
A P P O O M M A AA K K E
R A A PPPP OOO M M AA A K
K EEEE R P Layout
Drawing Utility ( From Compass MCP To Apollo
) -
Ver - by M.J.
KIM in DM Gr.
lambda
default lambda value is 0.3 pin
pin stretch length (micron) from
text coordinates to
boundary default pin stretch length is 1 lambda
spc pin to blockage spacing,
default is 1.5 Block M3 Feedthru Insert
Metal 3 Blockage (Y/N) , default No Must Join
Pin same name pins to be connected
externally in PR default
not connected (N) Extract for DLM default
is TLM or QLM (N) select
(Y) for DLM Case Sensitivity default is
Case Sensitive(Y) select
(N) for Case Insensitive
USAGE EXAMPLE lt
0.35um gt ApoMaker test.mcp TEST_MACRO test
0.2 0.2 1.0 Y N N Y Usage ApoMaker
mcpfile libraryname cellname lambda pin spc
Block M3 (Y/N) MJP (Y/N) Ext fot
DLM (Y/N) CASE (Y/N)
5
3.Design Library Creation? Reference Library ??
Flow
Create Design library with MilkywaygtLibrarygtCreat
e
Technology File
bpv.clf? ??
dbSetCellPortTypes (clfGetCLFLibName) (
(vdd POWER) (vss GROUND) ) f
CORE/IO Library
Design? ?? ?? ? ?? IO Library? _off_ ? ? ?.
2
1
Reference Created with MilkywaygtLibrarygtAdd Ref
4. Verilog Netlist? ??
(1) Cell Name? Pin Name? ????. (2) tri ?
wire ? ????. (3) tran ?? assign??? ?? ??. (
tran ( netA , netB ) - -gt assign netB netA
) (4) Module Name? .? ??? ? ??. ????
Aquarius? Netlist? ?? ? Module Name ? .NETL
???? ????. (5) Instance Name? Hierarchy
Separator(/)? ??? ?? ? VerilogIn??? ??? ???
???, Hierarchical Verilog Out?? ??? ??.
(1997.2.2.2.0.111 version??? .hvrc file?
???? Hierarchical Net Write? ???? ? ? ??? ???
??.) .hvrc? ?? escapedInst
U1/X1/X2/X3/U2/X5/X6/X7/U3 X1/X2/X3
escapedInst U1/X1/X2/X3/U2/X5/X6/X7/U3
X5/X6/X7 (6) Instance Name? Hierarchy
Separator(/) ? ??? ??? Collision? ???? ??
Verilog In? ? Hierarchy Separator( / -gt )? ????
Netlist? ????. (7) design?? floating pin? ????.
?? Verilog Netlist? floating Pin? ??? ???
Netlist Parsing?? ??? ? ? ??. (8) BUS assign?
??? ? macro cell? module??? ????. ???? Module? ??
??? ??? Routing? MSB? LSB? ?? ? ??. ?????
list file? ?? file? ?? ?? ???.
6
5. Netlist In Netlist Expand Flow
1. Verilog In (1) Netlist? File? ??? ??? Verilog
File? ?? ?? ? file? ??? List file? ????. (2) Bus
Naming Style? ????. (3) Logical High(1b1)?
Logical Low(1b0)? ?? Net Name? ??? ?? ??? Design
Flow??? ??? P/G Net Name? ????. (4) No Backslash
Insertion to avaoid Hier Name Collision? ????
Backslash? ????. (5) Bus Name Append? ?? ?? ????
??? ??. 2. Netlist Expand (1) Global Net Options
button? ??? ?? - P/G Net Name? Verilog
In?? ???? Net? ??? Net Name? ????. - P/G
Port Pattern? Regular Expression?? ???? logical
high? ARCSYS_LOGICAL_1?, logical
low? ARCSYS_LOGICAL_0? ??? ??. (2) LOG file??
deleted net? merged net? ????.
2
Translate netlist with MilkywaygtNetlist IngtEDIF
In or MilkywaygtNetlist IngtVerilog In
YES/NO
Hierarchical Netlist?
Expand netlist with MilkywaygtNetlist IngtExpand
Open Library in Apollo ApollogtLibrarygtOpen...
3
7
6. Design Set Up Flow
Rectilinear Design? ??
3
Optional
?? redraw ?? ?? !
Add rectilinear cell boundary on layer
255 ApollogtCreategtPolygon
Bind netlist and layout ApollogtDesign
Setup gtNetlistgtBind Netlist
Create the top-level cell ApollogtCellgtCreate
No Timing Driven
Optional
Timing Driven
Floorplan ApollogtDesign Setup gtFloorplangtSet Up
Floorplan
Set parasitic statistics ApollogtTiming Setup gtSet
Wire Utilization Estimate ApollogtDesign
Setup gtSet Wire Overlap Estimate
Load Tdf File Apollogt Design Setup gtTDFgtLoad TDF
Control Parameter ? Boundary? ? ??? Core ?
Boundary? offset Spacing? ??? ??
ApollogtTiming Analysis gtExtract
Overlap/Adjacency? ApollogtQuerygtList PR
Summary ?? ??? ??? ??
Floorplan ApollogtDesign Setup gtFloorplangtSet Up
Floorplan
Load TDF File ApollogtDesign Setup gtTDFgtLoad TDF
Control Parameter? ?? Ratio??? ?? ?? 0.6um HD
Library? ? ?? Double Back Option ??? ?? ?? row?
P/G Pin? Spacing? 0.75um ??? ?? ????.
Set Timing Model Linear or TLU ApollogtTiming
Setup gtTiming Options
Add Cell Rows ApollogtDesign Setup gtFloorplangtAdd
Rows by Area
Minimum Channel Height? Double Back Option? ??
?? Row Area? ????.
Path Constraints ? TDL?? Timing Requirements? ???
?? ?nternal? Path Constraints? Boundary
Condition? ??? ?? External? ????.
YES
Specify global net connections ApollogtPreRoute gtCo
nnect Ports to P/G
Timing Driven Layout?
4
P/G Net? Verilog In Expand Netlist ?? ???? ???
Net??? ????.
NO
5
8
7. Data Preparation for Timing Driven Layout from
Synopsys Flow
lt Synopsys gt
Synopsys Compiled Design(.db)
Write Path Constraints with write_constraints
-format sdf -cover_design -output
sdfFileName or write_constraints -format sdf
-max_nets 1 -max_paths numPaths -output
sdfFileName
4
OR
External Path Constraints
Internal Path Constraints
Write Timing Requirements with report_clock
-skew -nosplit gt reqFileName echo 1gtgt
reqFileName report_clock -attributes -nosplit gtgt
reqFileName echo 1gtgt reqFileName report_port
-nosplit -verbose gtgt reqFileName echo 1gtgt
reqFileName report_timing_requirements gtgt
reqFileName echo 1gtgt reqFileName report_design
gtgt reqFileName echo 1gtgt reqFileName
Write Boundary Conditions with report_clock
-skew -nosplit gt boundaryFileName echo 1gtgt
boundaryFileName report_clocks -attributes
-nosplit gtgt boundaryFileName echo 1gtgt
boundaryFileName report_port -nosplit -verbose
gtgt boundaryFileName echo 1gtgt boundaryFileName
Boundary Condition File
SDF Timing Constraints
Timing Constraints
Timing Requirements
Translate SDF to dbSetPathConstraint MilkywaygtNetl
ist Ingt SDF to Constraint
Create slack graph ApollogtTiming
Setup gtConstraints gtLoad Path Constraints
Create slack graph ApollogtTiming
SetupgtConstraintsgt gtLoad Timing Requirements
5
9
8. TDF file? ???? ???
lt ???? ??
?? gt 1. Pad placement constraints pad padName
padSide padOrder padOffset reflect pad
p2 top 3 pad p4 top 5 2000
reflect pad (dbConvertHierCellInstToLocal
(geGetEditCell) U0/U3/U153) left 3 2. Pin
creation command dbCreatePin cellId netId
pinName layerName pointArray dbCreatePin
(geGetEditCell) (dbGetNetByName (geGetEditCell)
VDD) VDD AL1 ((0,0),(0,0)) 3. Pin
placement constraints pin pinName layer width
depth pinSide pinOrder pinOffset pin p1
6 6 2 top 0 1500 lt- pin order(0)? ??? ?? ??
? pin p2-1 0 0 right 3 lt- pin
layer(-1)? ???? ??,
pin width? depth? ??
??? ? ?? 4. clock sourcese tdfSetClkDef
sourcePoint riseMin riseMax fallMin fallMax skew
period tdfSetClkDef CLKGEN/out 4.0 4.3 8.0
8.3 0.4 8.0 5. Net weight netWeight netName
netWtHorizontal netWtVertical netWeight CTL2
10 8 6. Design? Power Pad? ??? ?? insertPad
netName padCellName padName connectPin
insertPad VDD m1pad vdd1 PAD
insertPad GND m1pad gnd1 PAD 7. Power /
Ground / Clock Net? ?? markNet vdd POWER
markNet vss GROUND markNet clk
CLOCK
lt ???? ??? gt 1. Hierarchical cell instance name?
flat cell instance name?? ?? ?
dbConvertHierCellInstToLocal (geGetEditCell)
cellInstName 2. Hierarchical net name? local
name?? ?? ? dbConvertHierNetToLocal
(geGetEditCell) netName 3. Local cell instance
name? hierarchical cell instance name?? ?? ?
dbConvertLocalCellInstToHier (geGetEditCell)
cellInstName 4. Local net name? hierarchical
net name?? ?? ? dbConvertLocalNetToHier
(geGetEditCell) netName 5. Design? ?? Cell??
??? ? dbCreateCellInst (geGetEditCell)
masterLibName masterCellName
cellInstName rotation mirror origion
dbCreateCellInst (geGetEditCell) pvdb.FRAM
CPWPD 0 NO (0,0)
10
Corner Cell? ??? ? dbCreateCellInst
(geGetEditCell) pc45freul.FRAM CORNLT 0
NO (0 0) dbCreateCellInst (geGetEditCell)
pc45freur.FRAM CORNLB NO (0 0)
dbCreateCellInst (geGetEditCell)
pc45frell.FRAM CORNRT NO (0 0)
dbCreateCellInst (geGetEditCell)
pc45frelr.FRAM CORNRB NO (0 0) pad
CORNLT left pad CORNRT top pad
CORNRB right pad CORNLB bottom 6. ??
Net? Routing Width? ??? ? ? Route Rule? ???
? dbDefineVarRouteRule (geGetEditCell)
ruleSetName ((rule ) ... ) ?? Net? Rule?
??? ? dbAssignVarRouteRule (geGetEditCell)
ruleSetName ( netName ... ) ??
dbDefineVarRouteRule (geGetEditCell) wide (
(width metal1 1.0) (width metal2
1.0) (width metal3 1.0)
(spacing metal1 1.0) (spacing metal2 1.0)
(spacing metal3 1.0) )
dbDefineVarRouteRule (geGetEditCell) wider (
(width metal1 3.0) (width metal2
3.0) (width metal3 3.0) (spacing
metal1 3.0) (spacing metal2 3.0) (spacing
metal3 3.0) (contact via1 3 3)
(contact via2 3 3) )
dbAssignVarRouteRule (geGetEditCell) wide
(reset) dbAssignVarRouteRule
(geGetEditCell) wider (phi1 phi2) 7.
Design Cell?? ?? Net? Routing Layer? ??? ?
dbSetCellMinMaxLayer (geGetEditCell)
min_layer_name max_layer_name
dbSetCellMinMaxLayer (geGetEditCell) AL1
AL3 8. Design Cell?? ?? Net? Routing Layer?
??? ? dbAssignNetMinMaxLayer (geGetEditCell)
min_layer_name max_layer_name netNames
dbAssignNetMinMaxLayer (geGetEditCell) AL2
AL4 AAF., AAD. 9. Timing-Driven Spacing
Constraint? ? ?? ?? Net? ???? ???? Crosstalk?
intralayer coupling capacitance? ????.
dbAssignNetTimingSpacing (geGetEditCell)
(netName netName) dbAssignNetTimingSpacing
(geGetEditCell) (N4001 N46552) 10. Net
Criticality? ?? -gt wire length? ??? ( 0 not
critical 7 the most critical )
dbSetNetCriticality (geGetEditCell) netName
value dbSetNetCriticality (geGetEditCell)
PHI1 7 11. Rectilinear Design?? Pin Location?
??? ? dbSetPinLocation (geGetEditCell)
pinName layer pointArray dbSetPinLocation
(geGetEditCell) p1 AL1 ((0 10) (10 20))
11
9. Floorplanning Flow in Apollo
Optional
Place Macro Cells Automatically ApollogtPrePlace gtP
lace Macros
Unplace standard cells (keep macro placement
on) ApollogtPostPlace gtUnplace cells
Set drag flylines On for check cell
connections ApollogtOptionsgtFloorplanning
Optional
Place blocks ApollogtModifygtMove ApollogtModifygtTran
sform
Create groups ApollogtDesign SetupgtGroup gtAdd to
Group by Names
Create regions and assign group to
them ApollogtDesign Setup gtRegiongtCreate Region
Declare clock nets ApollogtClockgtSpecify Clock Net
Route clock trunks ApollogtPreRoutegtRectangular
Rings ApollogtPreRoutegtStraps ApollogtPreRoutegtCusto
m Wires
6
12
10. Placement Flow in Apollo
6
Optimization mode? Placement Constraint? Setting
Optional
rowend cell? ?? ??? axDeleteEndCap (geGetEditCell
)
Insert Rowend Cells with axAddEndCap
(geGetEditCell) drowend 1 f t
t axAddEndCap (geGetEditCell) drowend 2 t t
t
Set Placement Options ApollogtPlace gtPlacement
Common Options
User Padding? ? ?? File? ??? master Name
UnitTile instances patternName UnitTile
Place cells ApollogtPlacegtPlace Cells gtDesign
Placement
Define placement blockage ApollogtPrePlace gtPlaceme
nt Blockage gtCreate-Placement Blockage
Analyze congestion ApollogtPlacegtPlacement
Maps gtDisplay Placement Congestion Map
Optional
Improve Placement ApollogtPlacegtPlace
Cells gtSearchRefine Placement or ApollogtPlacegtPla
ce Cells gtArea Placement
Partition clock nets and insert clock tree
buffers ApollogtClock Tree gtSynthesize Clock Tree
Fill pad filler cells ApollogtPostPlacegt Add-Pad
fillers (filler.FRAM,overlap _filler.FRAM)

P/G Connections for additional
cells ApollogtPreRoute gtConnect Ports to PG
7
13
11. Power/Ground/Clock Pin Routing Flow in Apollo
Optional
Route cell Power/Ground/Clock pins ApollogtPreRoute
gtMacros/Pads ApollogtPreRoute gtStandard
Cells ApollogtPreRoute gtTop-Level Pins
Clock Tree Synthesis
Route last level of clock tree ApollogtRoute gtRoute
Net Group Route upper n-1 levels of clock
tree ApollogtClock gtZero Skew Routing
7
Check cell Power/Ground/Clock connectivity Apollogt
PreRoute gtVerify P/G Connectivity ApollogtClock gtVe
rify Clock Connectivity
8
12. Signal Routing Flow in Apollo
Global route ApollogtRoute gtGlobal Route gtGlobal
Route
Set Routing Options ApollogtRoute gtRoute Common
Options
8
??? ?? ??? Routing? ?? 1.Std-Cell ????
3??? OverFlow? 20???? Cluster? GRC?? ???
?? 2.? ???? 5??? OverFlow? ?? ?? 3.TLM?? Macro
Cell ??? Channel?? Metal3???? Over -Flow?
?? ??
Optional
Analyze congestion ApollogtGlobal Route gtDisplay
Congestion Map
Adjust Floorplan ApollogtDesign Setup gtAdjust
Floorplan
Assign tracks ApollogtRoute gtTrack Assign
Fix routing violations ApollogtRoute gtDetail
Route gtSearchRepair
Detail route ApollogtRoute gtDetail Route gtInitial
Detail Route
Optimize routing ApollogtRoutegtDetail
Route gtOptimize Routing
9
14
13. Verification Flow in Apollo
Run LVS ApollogtVerifygtLVS
Analyze LVS results
9
Fill Gap/Notch? ?? ?? ??? ??? Check Notch Option?
Off??. Ignore Same Net? On??.
Run DRC ApollogtVerify gtDRC
Analyze DRC results
10
14. PostLayout Flow in Apollo
Fill pad filler cells ApollogtPostPlace gtFiller
Cell gtAdd Pad fillers (filler.FRAM, overlap_filler
.FRAM)
Replace IO off Library to IO min/typ/max
Library MilkywaygtLibrary gtReplace
Ref or ApollogtLibrary gtReplace Ref
Design Update ApollogtCell gtForce Update!
11
Add Well Filler ApollogtPostPlacegtWell Filler gtAdd
Intra Row Well Filler ApollogtPostPlacegtWell
Filler gtAdd Inter Row Well Filler
To Change Reference Library to Physical Library
Fill Gap Notch ApollogtRoute Utility gtFill
Gap/Notch!
15
15. Replace Reference Library To Physical Library
Flow
?? MACRO Library? ??? GDS? ??? phantom? GDS?
MCP file? ???? Library? ????? ??? ?? Flow?
????.
MACRO Library
GDS Stream File
Read cell layout MilkywaygtCell LibrarygtStream In
Rename Cell ApollogtLibrarygtOpen ApollogtCellgtRename
NO
Cell Name? ??
YES
Design Library
Replace Reference with MilkywaygtLibrary gtReplace
Ref or ApollogtLibrary gtReplace Ref
Containing .FRAM (abstarct) .TIM
(timing) .CEL (not real physical) (_d
library)
Containing .FRAM (abstarct) .CEL (real
physical) (_h library)
16
16. Translating Apollo Library For Design Export
(1) Layer File? ?? ???? Layer File? Syntax?
??? ?? AquariusObjTypeAquariusNetType
AquariusLayer GDSIILayer GDSIIDataType ?? ???
??? ??? ??. A 255 63 0 (2) GDSII
Output MilkywaygtOutputgtStream Out Menu?
????. Stream File Name?????? ?? GDSII File
Name?, Library Name? Design? ???? ?? Library
Name?, Child Extraction Depth? 20?? ??,
Convert Option?? Specified Cell? ????, Cell
Name?? Top Design Name? ??. Flatten Option???
Via? Via Array? Flatten? ???? Option? On ???.
Fill Notch? Gap? ??? On? ??. ?? ??? Fill Notch
Gap? On ? ???? GDSII Out? ? ?? GAP, NOTCH Cell?
??? ? ? ??? Message? ??? Layout DB? Open??
AquariusBV? Apollo?? Fill Gap Notch? ?? ??? ???
??. Generate Instance Name As Prop ? Cell?
Instance Name? ????? ? ?? ???? Option? ?????
Instance Property Number? ??? ??? ??. Pin/Net
Options??? ?? Option? ? ?????.
17. Unconstrained ECO Flow
????? ???? Cell?? Placement ??? ???? ?? ??
Compare the ECO netlists and update the
layout MilkywaygtECO gtBy Net Compare
Translate the ECO netlistst MilkywaygtNetlist
IngtEDIF In or MilkywaygtNetlist IngtVerilog In
Expand netlist MilkywaygtNetlist In gtExpand
P/G Connections for additional
cells ApollogtPreRoute gtConnect Ports to P/G
Run ECO Placement ApollogtECO gtECO Place gtDesign
ECO!
Run ECO Routing ApollogtECOgt ECO Route!
17
18. Freeze Silicon ECO Flow
Cell?? ???? ?? metal? via mask pattern? ???? ? ??
lt Preparing Flow for Freeze Silicon ECO gt
ECO ??? ? Spare Cell?? Netlists? ???? Spare
Cell?? Input? Power? Ground Net? ????.
Translate the netlists MilkywaygtNetlist IngtEDIF
In or MilkywaygtNetlistgtVerilog In
Expand netlist MilkywaygtNetlistgtExpand
Create Spare Groups ApollogtDesign
SetupgtGroup gtAdd to Group by Name or ApollogtDesign
SetupgtGroup gtAdd to Group by Selected Set
Compare the ECO netlists and update the
layout MilkywaygtECO gtBy Net Compare
P/G Connections for additional
cells ApollogtPreRoute gtConnect Ports to P/G
Run ECO Placement ApollogtECO gtECO Place gtDesign
ECO!
Mark Spare Group ApollogtECO gtMark Spare Groups
Place Spare Cells ApollogtPostPlace gtSpread Group
Cells
Run ECO Routing ApollogtECO gtECO Route!
Command line? ?? ??? ???? Option?
????. axSetFreezeSiliconECO (geGetEditCell) t
18
lt Freeze Silicon ECO Flowgt
Compare the ECO netlists and update the
layout MilkywaygtECO gtBy Net Compare
Translate the ECO netlists MilkywaygtNetlist
IngtEDIF In or MilkywaygtNetlist IngtVerilog In
Expand netlist MilkywaygtNetlist In gtExpand
Run ECO Placement with Freeze Silicon
on ApollogtECOgtFreeze Silicon gtAuto Freeze Silicon
Auto!
P/G Connections for additional
cells ApollogtPreRoute gtConnect Ports to P/G
Run ECO Routing ApollogtECO gtECO Route!
19. Updating the Netlist for Layout Change Flow
ltPhysical Design?? ?? Hierarchical Netlist? ??? ?
??gt
Create Hierarchical Netlist MilkywaygtOutput gtCreat
e Hierarchical Netlist
Hierarchical Verilog Out MilkywaygtOutput gtHierarch
ical Verilog Out
Output Cell Name? ???? .HNET? ? ?.
ltSynopsys Backannotation Script? ??? ? ??gt
Generate Backannotaton Script MilkywaygtOutput gtGen
erate Backannotation Script
Create ECO DumpFile MilkywaygtECO gtWrite to File
Check ECO History MilkywaygtECOgtHistory
19
20. Timing Analysis - SDF Out -
Apollo gt Timing gt SDF .dc file? ?? ????
Expand hierarchical cells 97.2.2.2.0.113???
level 4?? ?? Transition delay on net TLU
timing model??? ?? ?? (off) Original Netlist
CTS ??? annotate ?? ?? ? on Interconnect
delay only Cell delay??? (CELL... (IOPATH)...))
?? ???
sdf file? delay data ??? ??? ??. (min1 typ1
max1) (min2 typ2 max2) ?? (min1 typ1
max1) ... (min6 typ6 max6)
1