G??sse? ?e????af?? ??????

1
G??sse? ?e????af?? ??????
2
G??sse? ?e????af?? ??????

• ?? ???sse? pe????af?? ?????? e??a?
  p??sa?at???sµ??e? st?? pe????af? t?? d?µ?? t??
  hardware ?a?/? t?? s?µpe??f???? t??
• ???s?µ?p?????ta? e????? ap? t? ß??µ??a??a
• ?p????? ?a ???s?µ?p???????
• ??a p??s?µ???s?
• ??a s???es?
• ???t?pe? ???sse? VHDL, Verilog

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?e????af? ?p?µ???d??

• S??ta?t??? 100 pe??p?? ??d???? ???e?? (input,
  output, wire, and, or, not ??p)
• // s????a
• ?e?? d?ast?µata a??????ta? d?????s? pe???,
  ?efa?a???
• ?as??? d?µ??? st???e?? ?p?µ???da (module)
• ?????eta? µe module .. endmodule

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Verilog pe????af? d?µ??
// Description of simple circuit module
smpl_circuit(A, B, C, x, y) input A, B, C
output x, y wire e and g1(e, A, B)
not g2(y, C) or g3(x, e, y) endmodule
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Verilog ?a??st???s? d??d?s?? p????
??a e?t??? µeta???tt?st? timescale timescale
1ns / 100ps d????e? ?t? µ???da µ?t??s?? t??
?a??ste??se?? e??a? t? 1ns ?a? ? a???ße?a ?at?
t?? st???????p???s? e??a? 0.1 ns
// Description of simple circuit module
smpl_circuit(A, B, C, x, y) input A, B, C
output x, y wire e and (30) g1(e, A,
B) not (10) g2(y, C) or (20) g3(x, e,
y) endmodule
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Verilog stimulus
// Stimulus module stimcircuit reg A, B, C
wire x, y smpl_circuit cwd(A,B,C,x,y)
initial begin A1b0 B1b0
C1b0 100 A1b1 B1b1
C1b1 100 finish end endmodule
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Verilog efa?µ??? d???µast???? e?s?d??
???.?????? ??s?d?? ???d?? (ns) A
B C y e x ?????? - 0 0 0 1 0
1 100 1 1 1 1 0 1 110 1 1 1 0 0
1 120 1 1 1 0 0 1 130 1 1 1 0 1
0 140 1 1 1 0 1 0 150 1 1 1 0 1 1
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???te??p???s? se ep?ped? p????
// Gate-level description 2-4-line decoder module
decoder_g1(A, B, E, D) input A, B, E
output 03D //d????sµa 4 bit wire
Anot,Bnot,Enot //es?te????? ??µß?? not
n1 (Anot, A), n2 (Bnot, B), n3 (Enot,
E) nand n4 (D0, Anot, Bnot, Enot),
n5 (D1, Anot, B, Enot), n6 (D2, A,
Bnot, Enot), n7 (D3, A, B, Enot) endmodule
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???te??p???s? ???? ?ed?µ????
// Dataflow description 2-4-line decoder module
decoder_df(A, B, E, D) input A, B, E
output 03D //d????sµa 4 bit assign
D0 (A B E), D1 (A B
E), D2 (A B E), D3 (A B
E), endmodule
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???te??p???s? S?µpe??f????
// Dataflow description 4-1 line MUX module
mux(i0, i1, i2, i3, select, y) input i0, i1,
i2, i3 input 10 select output y
reg y //? ???d?? t?? e?t???? p??pe? //?a
e??a? t?p?? reg always _at_ (i0 or i1 or i2 or
i3 or select) case (select) 2'b00
y i0 2'b01 y i1 2'b10 y
i2 2'b11 y i3
endcase endmodule

• st?? t?p? wire ? ???d?? µ?a? a???es?? a?a?e??eta?
  s??e???
• st?? t?p? reg ? t?µ? d?at??e?ta? µ????? ?t??
  a?ate?e? ??a t?µ?
• - ?? d?ad??as?a??? e?t???? e?te????ta? ???e f???
  p?? a????e? t?µ? ??p??a ap? t?? µetaß??t?? p??
  a?af????ta? µet? t? _at_