Graphical Design Environment for a Reconfigurable Processor

1
Graphical Design Environment for a Reconfigurable
Processor
Example Application using the
FPPA Multi-rate filter bank Each of the low
pass filters shown in figure 6 made up by the
four taps FIR filter with the debenchies
coefficient. Figure 6 shown a filter bank,
which is a portion of the circuit that implement
data compression using debenchies coefficient,
filter bank and the concept of wavelet
decomposition. For this example, especially
shown in figure 7 that FPPA can configure to be
the filter bank with ease through the help of the
simulink graphic interface. Down sampling at
each of the levels i.e. L1, L2, L3 and L4 are
accomplished by enable or disable desirable
processing element. Figure 8 shown the output
result at each of the down sample levels and the
source signal.
Abstract The Field Programmable
Processor Array (FPPA) is a new reconfigurable
architecture developed by NASA/GSFC and the
University of Idaho under ESTO funding. FPPA
architecture promises high-throughput,
radiation-tolerant, low-power data processing,
for spacecraft instruments. FPPA implements
a synchronous integer data flow computational
model, which is not easily captured in procedural
languages like C, but is easy to represent
graphically. This motivates our Simulink-based
design environment for the FPPA. In a process
familiar to all Simulink users, the algorithm
designer selects functional blocks from the menu,
places them on a work screen, and connects them
by drawing interconnect lines. A click of a
button executes the simulation. The goals of this
effort are to implement the following 1.
Verify algorithm this is the familiar Simulink
operational mode, which runs the simulation,
invoking underlying Matlab functions and
verifying the functional correctness of the
program. 2. Translate to FPPA
incorporating design parameters such as value
ranges and topology, the software will translate
the floating point Matlab representation to the
FPPA fixed point in an optimal fashion, and
generate an interface to the FPPASim simulator
software. 3. Verify the FPPA
implementation The designer now executes a
simulation that invokes the FPPASim program,
which faithfully duplicates the FPPA behavior.
4. Generate FPPA code when the
implementation has been verified, the software
will map the design to FPPA configuration and
run-time code, enabling the design to be ported
to FPPA chips.

• General model of the Processing Element
  (PE)
• Behavior of the PE
• The PE works in two different modes
• configuration and runtime.
• During the configuration mode
• C0, C1, Datapath and Runtime as shown
• in figure 4 are configures to a giving
• topology as well as a sequence of enable
• and disable of the PE.
• During the runtime mode, the PE take
• input data i.e. X,Y,W shown in figure 4
• and produce an output base on the
• configured topology as well as
• the status of the PE i.e. enable or disable.

• FPPA architecture
• An embedded data processor VLSI chip for
  spacecraft
• Radiation-tolerant, 0.25m CMOS process
• Fixed point processing elements
• Implements a reconfigurable synchronous data
  flow processor
• Run-time reconfigurable
• Extensible by tiling multiple chips
• Serves as accelerator to a host CPU
• Features
• 16 configurable on-board Processing Elements
• Four 16-bit-wide, bidirectional I/O ports
• One 16-bit-wide dedicated output port
• On-board program memory and execution unit
• Application development
• Text base development
• Configuration and Run-Time compilers