International Technology Roadmap

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International Technology Roadmap for
Semiconductors (ITRS 2000) Assembly
Packaging International Technical Working
Group December 6, 2000
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ITWG MEMBERSHIP
EUROPE Jean-Pierre Moscicki,
STMicroelectronics Bernd Roemer,
Infineon Co van Veen, Philips
TAIWAN Ho-Ming Tong, First Intl. Computer
Enboa Wu, ERSO/ITRI
KOREA S.Y. Kang, Samsung H.S. Chun,
Hyundai JAPAN Seiji Hamano, Fujitsu
Henry Utsunomiya, MITI
Consultant U.S. Alex Oscilowski,
Kulicke Soffa Bill Bottoms,
3rd Millenium Test Solutions John Prince,
University of Arizona Special
Topics Jurgen Wolf, Fraunhofer Chi Shih
Chang, Kulicke Soffa
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Scope

• System -on-a-chip (SoC) Packaging
• Wafer Level Packaging
• Mixed-signal and Radio Frequency Packaging
• Multi-Chip Packaging (MCP)
• Single Chip Packages (SCP)
• Flip Chip Interconnect (Direct Chip Attach (DCA)
• Bonding/Chip/Package/Substrate Design
• Chip Carrier Substrates
• Thermal Power/Ground Management
• Electrical/Performance Characterization
• Issues to be resolved in 2001
• how to distinguish between single chip packages,
  few chip packages/modules, MCP, and substrates

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Compatibility Between Roadmaps

• The ITRS AP roadmap and the NEMI packaging
  roadmap have been linked since 1996
• The ITRS roadmap provides much of the content for
  the NEMI packaging roadmap
• Both roadmaps were updated in 2000
• A majority of DTWG members are common
• The ITRS and the Jisso Roadmaps are closely
  coordinated
• The Jisso roadmap provides valuable chip,
  package, and board level data
• The Jisso chair and co-chair are ITWG members

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Typical Products by Sector
Note Major review of sectors planned for 2001
update
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Overall Industry Factors

• Communications markets, especially wireless, will
  equal and likely surpass PCs as the predominant
  end use market over the next 5 years
• chip and board level assembly are converging-
  this drives the need for amore comprehensive
  approach to technology and cost
• outsourcing continues to accelerate, and
  technology development continues to shift from
  OEMs to EMS providers and suppliers
• materials continue to dominate the cost of chip
  assembly and packaging

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Chip Packaging Factors

• Area array packages continue to experience CAGR
  2X industry average
• CSPs are growing faster than BGAs and are driving
  cost and technology (thin die,lt 0-.5mm ball
  pitch, etc)
• CSPs from Wafer Level Packaging (WLP) can shift
  the chip packaging paradigm and are limited by a
  lack of wafer level test/burn in capability
  (memory)
• chip interconnect will continue to drive
  packaging densification for all chip to next
  level connections (TAB, Wire bond and Flip Chip)
• chip interconnect is limited by substrate, probe,
  and encapsulation capability, all of which drive
  packaging cost

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Environmental Factors

• Pb free solder requirements are driving
  requalification of components, equipment, and
  materials at higher processing temperatures
• Elimination of Sb and Br from encapsulants and
  substrates requires the selection and
  qualification of suitable replacement materials
• Life cycle product management and take back
  requirements could drive changes in packaging
  design and material selection
• These factors are becoming requirements for doing
  business in Japan and Europe, could be
  differentiators in the U.S and have major cost
  implications

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Environmental Factor Cost Impact

• Low Cost and Memory segment Cost/pin have No
  Known Solutions beginning in 2001 due to
  environmental factors for most aggressive
  targets
• 10-15 cost Increases anticipated to accommodate
  
• Pb free solders
• Sb and Br free mold compounds and substrates
• new materials solutions should achieve roadmap
  cost targets in 12-18 months

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Difficult Challenges
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Assembly Packaging Technology Requirements
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2000 Changes

• Cost/pin
• Hand Held, Cost Performance
• upper range costs were lowered
• Hand Held, Cost Performance, Harsh, Memory
• cost labeled as No Known Solution due to
  increases which will be driven by new
  environmental materials
• Memory for 2001
• determine how to address memory categories for
  2001 update
• deal with increasing complexity
• incorporate performance memory

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2000 Changes

• Chip Size
• incorporated ORTC data
• cost-performance have minor changes
• high performance decreases 20-30
• memory increases 20-30
• determine how to address small chip issues that
  are highly cost sensitive (RF/mixed signal) in
  2001
• Power
• High Performance-minor increases
• Core Voltage
• Harsh- more rapid migration to 1.8V

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2000 Changes

• Pincount
• no changes
• Package Profile
• determine how to address stacked chips and
  thin/flexible packaging in 2001
• Performance on chip
• Cost Performance , High Performance- matched to
  Design ITWG values
• Memory- accelerated 166 and 200Mhz introductions
  for system memory and peripheral bus speed

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2000 Changes

• Performance chip to board
• Cost Performance- accelerated 166 and 200 Mhz
  introductions consistent w/ Memory changes
• need a new way to deal with game products
  (consider making it the high end of Low Cost) in
  2001
• new algorithm needed to relate chip to board and
  on chip performance targets in 2001 update

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2000 Changes

• Junction Temperature
• determine how to address need for 150 C junction
  for in cabin automotive application (add to Harsh
  or change another category in 2001 update)
• Operating Temperature
• no changes

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Key Issues for 2001

• Market sector redefinition
• cost of new environmentally friendly materials
• MEMS
• sensors (eg. Pressure and acceleration)
• relays (eg. Cell phone transmit/receive switch)
• Optical interconnect
• SCP, SIP, MCP,MCM, substrate distinctions
• Performance memory
• Gaming products- where do they fit?
• Stacked/ultra thin chip packaging
• Small chip issues (RF/mixed signal)

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Assembly Packaging Potential Solutions
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2000 Changes

• Chip to Next Level Interconnect
• aggressive acceleration of wire bond pitch
• 2001 2002 2003 2004 2005
• ball bond (um) 45 35 30 25 20
• wedge (um) 40 35 30 25 20
• some acceleration of area array flip chip
  pitches
• area array (um) 175 175 150 150 130
• peripheral (um) 150 130 120 110 100
• removed TAB-revisit in 2001 based on JISSO input
• add Flip Chip on Tape/Chip on Flex category

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Chip Interconnect Solutions
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Assembly Packaging Cross TWG Opportunities
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Cross TWG Opportunities for 2001

• Test
• AP TWG should
• add system level thermal modeling statement to
  text to address integrated AP/Test/Design issues
• discuss how to push industry to deliver thermal
  models for standard package types
• add thermal management recommendations
• review package electrical modeling section for
  high frequency with Design
• Test TWG should
• address pitch reduction issues for contactors
• address 1 Ghz issues with Design including
  package electrical models

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Cross TWG Opportunities for 2001

• Factory Integration
• the FI TWG agreed to add needs and potential
  solutions for AP and Test to provide
• unit level traceability
• mis-processing avoidance
• cycle time reduction
• improved equipment utilization

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Cross TWG Opportunities for 2001

• Interconnect
• develop a common section in both TWGs to address
  materials and integration issues
• Pete Elenius and Jurgen Wolf for AP
• Bob Gefken from Interconnect
• incorporate specific needs and solutions in the
  respective roadmap sections
• identify overall issues
• Cu wire bond
• bump technology with low k
• determine which issues are specific vs common
• act on issues/incorporate in 2001

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Summary

• Linkages between ITRS, NEMI, and Jisso roadmaps
  help provide a unified message to the industry
• major changes to date include
• chip size for cost-performance, high-performance,
  memory
• accelerated memory performance and related impact
  on cost-performance segment
• accelerated wire bond pitch
• linkages with other TWGs require follow up
• unresolved issues to be addressed in 2001update
  are an opportunity to further improve the quality
  and impact of the ITRS
• active participation from all regions is key to
  success