Lect 5: Protected-Mode Software Architecture

1
Lect 5 Protected-Mode Software Architecture
2
Protected-Mode Register Model

• GDTR global descriptor table
• LDTR local descriptor table
• IDTR interrupt descriptor table
• TR task register
• EIP 32 bits in length
• EFLAGS
• CR0, CR1, CR2, CR3
• DR0-DR7(Debug registers)
• TR6-TR7(Test registers)

EIP
CS DS SS ES FS GS
AX BX CX DX
SP BP SI DI
DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7
EFLAGS
0
47
15
16
Limit
Base
GDTR IDTR LDTR
Base
Limit
MSW
CR0 CR1 CR2 CR3
TR6 TR7
TR
3
Segment Descriptors

• Descriptor
• the element by which the on-chip memory manager
  hardware manages the segmentation of the
  80386DXs 64T-byte virtual memory address space.
• One descriptor exists for each segment of memory
  in virtual address space.
• 8 bytes long and contains three kinds of
  information
• Limit
• Base
• Access Rights
• Types of segment descriptors
• system segment descriptor(s0), non-system
  segment descriptor(s1)(code and data)

4
Segment Descriptors
23
16
15
8
7
0
32
24
AVL
4
BASE 31..24
G
X
0
P
DPL
S
TYPE
A
BASE 23..16
LIMIT 19..16
7
SEGMENT LIMIT 15 .. 0
3
SEGMENT BASE 15 .. 0
0
5
Global Descriptor Table

• Global Descriptor Table
• GDT provides a mechanism for defining the
  characteristics of the 386 global memory address
  space. Global memory is a general system resource
  that is shared by many or all software tasks.
• contains system segment descriptors

8191
Global Descriptor Table (GDT)
Global Descriptor Table Register(GDTR)
MAX 64k bytes 8K entries
16
15
47
0
LIMIT
BASE
1
0
6
Interrupt Descriptor Table

• Interrupt Descriptor Table (IDT)
• contains interrupt descriptors, not segment
  descriptors
• IDT can also be up to 64KB But 386 only supports
  up to 256 interrupts and exceptions(2KB)

255
Interrupt Descriptor Table (IDT)
Interrupt Descriptor Table Register(IDTR)
MAX 2k bytes 256 entries
16
47
15
0
LIMIT
BASE
1
0
7
Local Descriptor Table

• Local Descriptor Table
• Each task can have access to own private
  descriptor table(LDT) in addition to GDT.
• contains descriptors that provide access to code
  and data in segments of memory

15
0
GDT
GDTR
LIMIT
31
BASE
15
0
LDTR

selector
LDT0
LDTR cache
0
15
LIMIT
31
BASE
program invisible

LDTn
8
Control Registers
MP math present EM emulate R extension
type TS task switched

• MSW CR0
• the lower 5 bits of CR0 are system-control flags
• PE protected-mode enable bit
• At reset, PE is cleared.(real mode)
• Set PE to 1 to enter protected mode
• Once in protected mode, 386 cannot be switched
  back to real mode under SW control

9
Control Registers and Task Register

• Paging mechanism
• MSB of CR0, CR2, CR3
• Task Register
• task switching mechanism
• TSS descriptor
• TSS task state segment information needed to
  initiate the task, such as initial values for the
  user-accessible registers

Physical Memory
TSS descriptor
TR
GDT
16
47
0
15
BASE
LIMIT
TSS
10
Register With Changed Functionality
SEGMENT SELECTOR REGISTER
T I
RPL
INDEX
Requested Privilege Level(RPL)
Indicates selector privilege level desired
1-0
TI0 use global descriptor table (GDT) TI1 use
local descriptor table (LDT)
Table Indicator (TI)
2
15-3
Index
select descriptor entry in table

• Example CS 1007H, GDT base 00100000H, LDT base
  00120000H
• (CS) 0001 0000 0000 0111 RPL 3, TI 1,
  Index 0001 0000 0000 0
• Address of the segment descriptor 00120000H
  1000H 00121000H

11
EFLAGS
7
15
0
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0
V R 0 N IO O D I T S Z 0 A 0 P 1 C M F T PL
F F F F F F F F F

• VM virtual 8086 Mode - system flag
• set only in Protected Mode by IRET instruction
  and by task switches
• unaffected by POPF
• RF resume flag - system flag
• in conjunction with the debug register
  breakpoints
• NT nested task flag - system flag
• indicates that the execution of this task is
  nested within another task
• IOPL input/output privilege flag - system flag
• indicates the numerically maximum CPL value
  permitted to execute I/O instructions

12
Protected Memory Management and Address
Translation

• Virtual Address and Virtual Address Space
• virtual address selector(16-bit)
  offset(32-bit)
• 214(16,384 16K) unique segments of memory, each
  of which has a maximum size of 4G bytes
• Total virtual address space 246 , 64 TB

0
47
32
31
offset
selector
T I
RPL
INDEX
13
Protected Memory Management and Address
Translation

• Segment Partitioning of the Virtual Address Space

Local segment 8191
Local address space 32 Terabytes
Local segment 1
Virtual Address Space 64 Terabytes
Local segment 0
Global segment 8191
Global address space 32 Terabytes
Global segment 1
Global segment 0
14

• Application Program a collection of tasks
• task a group of program routines that together
  perform a specific function
• A task can activate both global and local
  segments of memory

Task 1 Local Address Space
Task 1 Virtual Address Space
Global Address Space
Task 3 Virtual Address Space
Task 2 Virtual Address Space
Task 2 Local Address Space
Task 3 Local Address Space
15
Physical Address Space and Virtual-to-Physical
Address Translation
SELECTOR
OFFSET
LOGICAL ADDRESS
SEGMENT TRANSLATION
PG?
PAGING DISABLED
PAGING ENABLED
0
31
DIR PAGE
OFFSET
LINEAR ADDRESS
PAGE TRANSLATION
PHYSICAL ADDRESS
16
Segmentation Virtual to Physical Address
Translation
OFFSET
SELECTOR
LOGICAL ADDRESS
Selector Offset(EBX)
(DS)
SEGMENT TRANSLATION
Data Segment
PG?
PAGING DISABLED
Operand
PAGING ENABLED
0
31
DIR PAGE OFFSET
LINEAR ADDRESS
PAGE TRANSLATION
Data Segment Descriptor Cache Register
LDT
Segment Descriptor
PHYSICAL ADDRESS
17
Segment Selector Register and the Cache Registers
Transparently Loaded by MPU
Programmer accessible Selectors
Access Rights
Base Address
Limit
CS

DS
64-bit Segment Descriptor Cache Registers
SS
ES
FS
GS
0
19
20
51
52
63