Yawgeng Chau

1
Logic Circuit Design

• Yawgeng Chau

2
Contents

1. Binary Systems
2. Boolean Algebra and Logic Gates
3. Gate-Level Minimization
4. Combinational Logic
5. Synchronous Sequential Logic
6. Registers and Counters
7. Memory and Programmable Logic

3
5.1 Sequential Circuits

• Sequential circuits consist of
• Input, logic gates, output, storage elements
• State of storage elements is a function of past
  input
• Output depends on current and past inputs.
• State binary information stored in memory
• Sequential circuit is specified by
• A time sequence of inputs, outputs, and internal
  states.

4
5.2 Synchronous vs. Asynchronous

• Synchronous Sequential Circuit
• Function according to its inputs and states at
  discrete instants of time.
• Asynchronous Sequential Circuit (Ch. 9)
• Function according to its inputs and states at
  discrete instants of time and the input changing
  order.
• May become unstable due to feedback.

5
Synchronous Clocked Sequential Circuit

• Use clock generator to generate a periodic train
  of clock pulses.
• Storage elements are activated when a clock pulse
  arrives.
• States can change during pulse transition.

6
Flip-Flops as storage elements

• Flip-flop binary storage device to store 1bit.

7
5.3 SR Latch with NOR Gates

• S or R must go back to 0 before further changes
  to avoid undefined states.
• 1 should not on S and R at the same time.

R1 Reset State
Forbidden
8
SR Latch with NAND Gates

• S or R must go back to 1 before further changes
  to avoid undefined states.
• 0 shouldn't go on S and R at the same time.

S0 Set State
Forbidden
9
SR Latch with Control Input

• Enable signal is used to determines when the
  state of the latch can be changed.

En1 enable En0 disable
10
D Latch

• To ensure that S and R never equal to 1 at the
  same time.
• Transparent latch temporary bit storage

11
Graphic Symbols
SR Latch with NAND gates
NOR gates
12
Latch Problem from Feedback (1/2)
Unpredictable results if En1 with changing D
13
Latch Problem from Feedback (2/2)

• Latch state changes once the clock pulse changes
  to 1.
• New latch state appears at the output while the
  pulse is active.
• The output works on the latch input through
  combinational feedback.
• If inputs change while the clock pulse is in 1,
  the latch will respond and result in new outputs.

14
5.4 Flip-Flops (1/2)

• Flip-Flop (FF) a memory element changes at the
  edge of clock only
• If level-triggered flip-flops are used
• The feedback path may cause instability problem
• Edge-triggered flip-flops
• The state transition happens only at the edge
• Eliminate the multiple-transition problem

15
Flip-Flops (2/2)

• Trigger Change in control input.
• Triggered only during a signal transition.

Level trigger
Positive trigger or rising-edge trigger
Negative trigger or falling-edge trigger
16
D Flip-Flops
Q(t1)D

• Work as D-latch, but edge-trigger

Characteristic Table
Fig. 5.11 Graphic symbols for edge-triggered D
flip-flop
17
Master-Slave D Flip-Flop (1/2)

• Negative-edge trigger

Slave Q doesnt change
Master D?Y
Y doesnt change
Y?Q
18
Master-Slave D Flip-Flop (2/2)

• How to make it be a positive-edge triggered
  flip-flop?

19
D-Type Positive-Edge Triggered Flip-Flop

• Initially, CLK0, S1,R1 Q(t1)Q(t)
• When CLK?1 as D0, R?0, Q0
• If D changes to 1
• when CLK1, R0
  because Q0
• When CLK?1
• as D1, S?0, Q1
• If D changes to 0
• when CLK1, S0.

20
Time Parameters

• Setup Time minimum time such that D must be
  maintained at a constant value before clock
  transition.
• Hold Time minimum time such that D does not
  change after the positive clock transition.
• Propagation Delay Time time from trigger edge to
  the time of a stable output.

21
JK Flip-Flop
Q(t1) D JQ(t)' K'Q(t)
22
T Flip-Flop
T0, DQ(t) , Q(t1)Q(t) T1, DQ'(t) ,
Q(t1)Q'(t)
T0, JK0, Q(t1)Q(t) T1, JK1, Q(t1)Q'(t)
Q(t1)T?Q(t)
23
Characteristic Tables
24
Characteristic Equations
K 0 1
J 0 1
Q(t) 0
1 Q'(t)
Q(t1)J'K'QJK'JKQ'J'K'QJK'QJK'Q'JKQ'
K'QJQ'
25
Preset Clear (Reset)

• Asynchronous input

R0 clear R1 undo
1 1
26
5.5 Analysis

• Given a sequential circuit, we try to guess what
  it is.
• Step 1 write the excitation equations or the
  state equations
• Step 2 draw the state table
• Step 3 draw the state diagram
• Step 4 guess
• All red keywords have the same meaning.

27
Flip-Flop Input/Output Equations
flip-flop input
DA
flip-flop name
Step 1 (way 1) Compute input equation (or
called excitation equation) output equation

• DA Ax Bx
• DB A'x
• y (AB)x'

28
Next-State Derivation

• Step 1 (Way1) determine input equations (or
  excitation equations) using present states and
  input variables.
• Step 2 list all binary combination of
  inputs/state. Use characteristic table to
  determine next state values and create the state
  table.

29
State Equations
A
DAAxBx
x
Step 1 (way 2)
x
excitation or input equation
B
DA A x B x DB A' x
output equation
y (AB)x'
A'
DBA'x
characteristic equation
x
Q(t1)D
state equation
A(t1) DA A x B x B(t1) DB A' x
B
yx'(AB)
A
x'
x
30
State Table (1/2)
Step 2 Draw the state table
(form 1)
(1) excitation equ.

• DA Ax Box
• DB A'x
• y (AB)x'

DADB A B
00 01 00 11 00 10 00 10
00 01 00 11 00 10 00 10
(2) state equ.
A(t1) Ax Bx B(t1) A'x y(t) (AB)x'
31
State Table (2/2)
Step 2 Draw the state table
(form 2)
32
State Diagram
Step 3 Draw the state diagram
AB
State
Mealy Machine
33
Example of D Flip-Flop
Step 1 excitation equation or state equation
DAA?x?y
x?y
Step 2 state table
Step3 state diagram
34
Example of JK Flip-Flop (1/3)
Step 1 excitation equation
JA B KABx' JB x' KBA?x
JAB
x'
KABx'
B
JBx'
A
KBA?x
x
35
Example of JK Flip-Flop (2/3)
Step 2 state table
JA B KABx' JB x' KBA?x
36
State Equations Derived with Characteristic
Equations and Input Equations
characteristic equation
Q(t1) D JQ(t)' K'Q(t)
?
State equations
JAB
A (t1) JAA' KA'A BA' (Bx')'A A'B
AB' Ax
KABx'
JBx'
B (t1) JBB' KB'B x'B' (A?x)'B B'x'
ABx A'Bx'
KBA?x
37
Example of JK Flip-Flop (3/3)
Step3 state diagram
38
Example of T Flip-Flop (1/3)
x
TABx
yAB
B
Step 1 characteristic equation
input/output equation
TBx
state equation
39
Example of T Flip-Flop (2/3)
Step 2 state table
TA Bx TB x y AB
TATB A B
00 01 01 10 10 11 11 00
40
Example of T Flip-Flop (3/3)
Step 3 state diagram
Input
AB / y
State/output
Moore Machine
41
Mealy FSM (Finite State Machine)

• Output is a function of input and present state.
• For synchronized output, inputs are synchronized
  with the clock.
• Outputs must be sampled during the clock edge.

yx'(AB)
42
Moore FSM
x
TABx
yAB
B

• Output is a function of present state only.
• Outputs are synchronized with the clock.

TBx
43
5.7 State Reduction

• To reduce the flip-flop number.
• May require more combinational gates.

Design a ciruit Step 1 Draw the state diagram
but find the graph is complex
44
Example (1/5)

• state a a b c d e f f g f g a
• input 0 1 0 1 0 1 1 0 1 0 0
• output 0 0 0 0 0 1 1 0 1 0 0

45
Example (2/5)
Step 2 Draw the state table
46
Example (3/5)

• States g and e are equivalent.

g is replaced by e.
Step 2 Find two equivalent states,
replace one with another,
redraw the
state table
47
Example (4/5)

• States f and d are equivalent.

f is replaced by d.
Step 3 Repeat Step 2 until you can not find any
more
48
Example (5/5)
Step 4 Redraw the state diagram
49
State Assignment
Step 5 State assignment Redraw the state table
?
50
5.8 Simplified Design Procedure

• Step 1 Derive a state diagram from operation
  specifications.
• Step 2 Obtain the state table by finding the
  input values of flip-flops.
• Step 3 Derive input equations and output
  equations.
• Step 4 Draw the sequential circuit

51
Example 111 sequence detector

• Detect the occurrence of three or more
  consecutive 1s.
• S0 more than one 0 appear.
• S1 one 1 appears.
• S2 two 1s appear.
• S3 three 1s appears.

S0?00 S1?01 S2?10 S3?11
Step 1 Draw the state diagram
52
Synthesis with D Flip-Flop (1/3)
Step 2 Draw the state table by finding the input
values of D-FFs

• Use two D flip-flops to represent 4 states.
• State (A,B)
• input x, output y

Step 3 Derive input equation output equation
DA(A,B,x)A(t1) ?(3,5,7) DB(A,B,x)B(t1)
?(1,5,7)
y(A,B,x) ?(5,7)
53
Synthesis with D Flip-Flop (2/3)
Step 3 Simplify input equation output equation
54
Synthesis with D Flip-Flop (3/3)
Step4 Draw sequential cricuit
55
Synthesis with JK Flip-Flop (1/3)
Given the half state table
Step 1 skips
Step 2 to find the input values of JK-FFs
56
Excitation Table for JK Flip-Flops

• The table lists required inputs for a state
  change. Obtained from the characteristic table.

Dont Care
57
Synthesis with JK Flip-Flop (2/3)
Step 3 Derive input equation output equation
58
Synthesis with JK Flip-Flop (3/3)
Step 4 Draw sequential circuit
59
Synthesis with T Flip-Flop (1/4)

• Example 3-Bit Binary Counter
• Input clock
• Output next state

Step 1 Draw the state diagram
60
Synthesis with T Flip-Flop (2/4)

• A2, A1, A0 Three flip-flop outputs.

Step 2 Draw the state table
61
Excitation Table for T Flip-Flops

• The table lists required inputs for a state
  change. Obtained from the characteristic table.

62
Synthesis with T Flip-Flop (3/4)
Step 3 Derive input equation output equation
63
Synthesis with T Flip-Flop (4/4)
Step 4 Draw sequential circuit
64
Design Procedure

1. Derive a state diagram from operation
   specifications.
2. Reduce state numbers.
3. Assign binary codes to states.
4. Obtain the state table.
5. Choose the flip-flop type.
6. Derive input equations and output equations.
7. Draw the sequential circuit.

65
Synthesis Procedure

• Step 1 is completed by designers.
• Steps 2 and 3 are seldom used.
• Step 4 to step 7 can be implemented using HDL and
  automatic synthesis tools (Electronic Design
  Automation (EDA) tools).
• To obtain synthesis netlist.

66
Home Works

• Read Section 5-5
• Problems 5-2, 5-4, 5-6, 5-7, 5-8, 5-10, 5-12,
  5-16, 5-19