Hassan Mostafa

1
Statistical Timing Yield Improvement of Dynamic
Circuits Using Negative Capacitance Technique

• Hassan Mostafa M. Anis M. Elmasry
• University of Waterloo, Ontario, Canada

2
Outline

• Introduction and Background
• Motivation and Objectives
• Negative Capacitance Circuits
• Statistical Timing Yield Improvement Using
  Negative Capacitance
• Results and Discussions
• Conclusion

Introduction and Background
3
Outline

• Introduction and Background
• Variability
• Wide Fan-in Dynamic OR gate
• Motivation and Objectives
• Negative Capacitance Circuits
• Statistical Timing Yield Improvement Using
  Negative Capacitance
• Results and Discussions
• Conclusion

Introduction and Background
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Variability Classification

• Die-to-Die (D2D)
• Affects all devices on the chip in the same way
• e.g., all devices on a chip have the same Vt
• Within-Die (WID)
• Variations within a single chip
• Affecting devices on the same chip differently
• e.g., devices on the same chip have different Vt

Introduction and Background
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Design Methodologies
(Overhead)
Introduction and Background
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Process Variations Sources

• Random Dopant Fluctuations (RDF)
• As CMOS devices are scaled, number of dopant
  atoms decreases
• The number of dopant atoms has variations around
  its nominal value resulting in Vt variations
• sVt a (WL)-0.5
• As transistor area decreases with scaling, sVt
  increases
• Channel Length Variation
• Difficulty to control the critical dimensions at
  sub-wavelength lithography
• Large variations in the channel length (L)
• Vt a exp(-L) due to short channel effects
• A small variations in L results in large
  variations in Vt

S. Borkar et al., DAC04
Variations increase with technology scaling
Introduction and Background
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Variability and Yield

• Process variations causes the device parameters
  to have fluctuations around their nominal values
• The system parameters such as delay and power
  have a spread around their nominal values
• This result in a percentage of the systems does
  not meet the required function or the required
  parameter constraint
• ? Yield loss

Variability results in Yield loss
Introduction and Background
8
Wide Fan-in Dynamic OR Gate

• Used in the processor critical path
• Wide Fan-in (i.e., 16-input dynamic OR gate)

Wide Fan-in Dynamic OR gates are essential for
high performance processor modules
Introduction and Background
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Wide Fan-in Dynamic OR Gate

• Keeper transistor design
• Small W/L
• To avoid delay and power increase due to
  contention
• Large W/L
• To hold the floating output node at VDD against
  the increased leakage currents, especially, with
  technology scaling

With technology scaling, the increased leakage
and variability result in larger delay and power
Introduction and Background
10
Wide Fan-in Dynamic OR Gate

• Timing yield improvement techniques
• Keeper control circuits
• Digitally controlled keeper sizing
• Large leakage ? Large keeper W/L
• Small Leakage ? Small keeper W/L
• Body bias controlled keeper sizing
• Large leakage ? Smaller keeper Vt
• Small leakage ? Larger keeper Vt
• These techniques utilize
• a leakage current sensor (analog)
• Analog to digital converter
• Digital control circuit

Previous timing yield improvement techniques
exhibit large area overhead? Negative capacitance
to the rescue
Introduction and Background
11
Outline

• Introduction and Background
• Motivation and Objectives
• Negative Capacitance Circuits
• Statistical Timing Yield Improvement Using
  Negative Capacitance
• Results and Discussions
• Conclusion

Motivation and Objectives
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Motivation and Objectives

• Wide Fan-in dynamic OR gates are essential blocks
  in high performance processor modules
• The increased variability and leakage result in
  timing yield loss
• The existing timing yield improvement techniques
  exhibit large overhead (area and power)
• Main idea
• Delay a Output Capacitance
• Dynamic Power a Output Capacitance

Reducing the output capacitance reduces the delay
and the dynamic power
Negative capacitance breaks the power-performance
trade-off
Motivation and Objectives
13
Outline

• Introduction and Background
• Motivation and Objectives
• Negative Capacitance Circuits
• Statistical Timing Yield Improvement Using
  Negative Capacitance
• Results and Discussions
• Conclusion

Negative Capacitance Circuits
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Negative Capacitance Circuits

• 1- Miller effect based circuit

Differential Amplifier
Buffer Amplifier
Negative Capacitance Circuits
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Negative Capacitance Circuits

• 2- Negative Impedance Converter (NIC) based
  circuit

For Current conveyor NIC,
Current Conveyor
Negative Capacitance Circuits
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Negative Capacitance Circuits

• The buffer amplifier based negative capacitance
  circuit
• A higher supply voltage is needed (VDDH)
• High Vt transistors to reduce the static power
  consumption

VDDH
VDDL
VDDH
VDDL
Negative Capacitance Circuits
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Outline

• Introduction and Background
• Motivation and Objectives
• Negative Capacitance Circuits
• Statistical Timing Yield Improvement Using
  Negative Capacitance
• Results and Discussions
• Conclusion

Statistical Timing Yield Improvement
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Statistical Timing Yield Improvement Using
Negative Capacitance

• Timing yield improvement

n 3 for YO 99.87
Statistical Timing Yield Improvement
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Outline

• Introduction and Background
• Motivation and Objectives
• Negative Capacitance Circuits
• Statistical Timing Yield Improvement Using
  Negative Capacitance
• Results and Discussions
• Future Work
• Conclusions

Results and Discussions
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Results and Discussions

• 16-input OR gate is used
• The target delay (AO) 102.4 psec and s 10.61
  psec
• The output capacitance Cout 9.38 fF and the
  constant ? 10.92 psec/fF.
• The required negative capacitance CNEG - 2.9
  fF is realized by
• Using the buffer amplifier, A 30 and CF 0.1 fF
  
• Using the differential amplifier, A 3.9 and CF
  1 fF
• Using the current conveyor, CL 2.9 fF

Results and Discussions
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Results and Discussions
Target Delay

• 5000 Monte Carlo
• Timing yield 100
• Mean delay reduction by 31
• OR gate power reduction by 10
• Delay standard deviation reduction by 58
• All the three proposed negative capacitance
  circuits provide similar results

Results and Discussions
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Results and Discussions

• Why the delay standard deviation reduction is
  reduced?
• ?AO ?? X Cout
• ?AO ?? X Cout
• Since Cout gt Cout
• Stability
• The OR gate becomes unstable when CNEG gt Cout
  (i.e.,Coutlt 0 ), which will not happen because
  AO is always positive.

?AO gt ?AO
Results and Discussions
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Results and Discussions

• Power overhead
• The buffer amplifier (CF 0.1 fF)
• No power overhead (power saving of 5)
• Dual supply voltage and high Vt transistors
  needed
• The differential amplifier (CF 1 fF)
• Power overhead 5
• Limited by the constant gain-bandwidth product
• The current conveyor (CL 2.9 fF)
• Power overhead 30
• Suitable for high frequency applications ( No
  constant gain-bandwidth product limitation)

Results and Discussions
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Outline

• Introduction and Background
• Motivation and Objectives
• Negative Capacitance Circuits
• Statistical Timing Yield Improvement Using
  Negative Capacitance
• Results and Discussions
• Conclusion

Conclusion
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Conclusion

• A negative capacitance circuit is introduced for
  timing yield improvement in wide fan-in dynamic
  OR gates.
• All the proposed negative capacitance circuits
  improve the timing yield (by reducing the mean
  delay), reduce the delay variability by 58, and
  reduce the OR gate power by 10.
• The buffer amplifier circuit exhibits no overhead
  (5 total power saving) but a dual supply voltage
  and high-Vt transistors are required.
• The differential amplifier and the current
  conveyor circuits have power overhead of 5 and
  30, respectively.

Conclusion
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• THANK YOU

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64-input OR gate
Buffer Amplifier CNEG
Differential Amplifier CNEG
NO CNEG
Current Conveyor CNEG
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64-input OR gate