Reducing Voltage Supply

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Reducing Voltage Supply

• Jins Davis Alexander

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Objective

• To reduce the power consumption by reducing VDD
  supply voltage and seeing its effect on power,
  delay and area.
• No effect on area.

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What We Know.

• Power Consumption is a quadratic function of
  Voltage.
• Decrease in supply Voltage increases the overall
  delay.

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Power and Delay

• Power CVDD2
• Delay KVDD
• -------
• (VDD Vt)a
• (from alpha-power model)

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What I have done

• Designed NN array multiplier using VHDL.
• Used ELDO for power analysis and calculation of
  delay.
• First simulated basic cell and found delay of
  Sumout to be greater than Cout.

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• Forced pulse signals for all possible vectors at
  inputs A and B for a 4x4 multiplier.
• Compared signal A0 with Sum2N-2 to calculate
  the overall worst case delay.

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Results of 4x4 array multiplier.
Voltage Avg.Power (uW) Delay (ns)
1.8 106.32 1.76
1.5 66.43 1.934
1.2 36.49 2.34
1 21.71 3.99
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Results
Voltage( Decrease) Avg Power( Decrease) Delay ( Increase)
16.7 37.5 10
33.3 65.6 33
44.4 79.5 127
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Dynamic Power vs. Voltage
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Delay vs. Voltage
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Static Power vs. Voltage
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Conclusion.

• Reducing Voltage decrease power significantly.
• However at lower voltages the delay increase is
  very significant.
• Transistor sizing, parallel processing can help
  reduce the overall delay.

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• THANK YOU.