Dual-Voltage Supply for Power Reduction

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Dual-Voltage Supply for Power Reduction

• ELEC 6970 Low Power Design
• Project Presentation
• by
• Muthubalaji Ramkumar

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Problem Statement

• To Use a dual-supply voltage in order to reduce
  the power consumption of the 32 x 32 bit
  integer array multiplier circuit without
  compromising the overall delay

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Power and Delay

• Power ? VDD2
• Delay ? KVDD
• -------
• (VDD Vt)a

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Approach

• Low Voltage Assignment to as many cells as
  possible
• The interconnections in this multiplier circuit
  makes it difficult
• Therefore assign Low Voltage Supply to as many
  gates as possible

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Things to watch

• Reducing the Voltage Supply will increase the
  delay of a gate
• Therefore assign Low-Voltage Supply only to the
  gates which do not have any influence on the
  Critical Path Delay directly or indirectly
• Low voltage gate should have adequate voltage
  swing in order to drive a High Voltage gate its
  feeding in to.

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4 x 4 Multiplier
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Multiplier Cell
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Low-Voltage Supply Assignment
Output Cells along the edge N-1 G4
First Row 3(N-1) G1,G2,G3
Second Row to Last Row N(N-1) G1
Left Column 2(N-1) G2,G3
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• Total Number of gates 6N2
• Number of gates with Low Voltage
• assignment (N-1)(N6)
• Percentage of the circuit with Reduced VDD
• (N-1)(N6) / 6N2

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Percentage of the Circuit with Reduced Voltage
Supply
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Experimental Results for a Cell
Voltage (Volts) Pdyn (Microwatts) Pstatic (Picowatts) Delay (Sec)
1.8 9.1 246 251 p
1.5 5.27 171 358 p
1.2 2.87 112 537 p
0.9 0.79 67 1.14 n
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Experimental Results for a 4 x 4 Multiplier
Voltage (Volts) Pdyn (Microwatts) Pstatic (Nanowatts) Delay (Sec)
1.8 213 1.6 1.57 n
1.5 132.1 1.13 1.76 n
1.2 75.8 0.75 1.97 n
0.9 36.4 0.46 2.2 n
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A Single Inverter
Voltage (Volts) Pdyn (Microwatts) Pstatic (Picowatts) Delay (Sec)
1.8 1.88 10 82 p
1.5 0.588 7 91 p
1.2 0.114 4.6 108 p
0.9 0.047 2.8 236 p
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4 x 4 bit array Multiplier

• N4
• Total Number of Gates 6N2 6(16) 96
• Number of Gates with Low VDD (N-1)(N6)
• (3)(10) 30 31.25
• Number of Gates with Normal VDD
• 96 30 66 68.75

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Power Estimation

• Using Dual-Voltages, 1.8V 1.5V
• Power Consumption
• (0.3125)(132.1uW) (0.6875)(213uW)
• 187.73 uW
• 12 Power Reduction

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Power Estimation

• Using Dual-Voltages, 1.8V 1.2V
• Power Consumption
• (0.3125)(75.8uW) (0.6875)(213uW)
• 170.125 uW
• 20.13 Power Reduction

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32 x 32 bit array Multiplier

• N32
• Total Number of Gates 6N2 6(1024) 6144
• Number of Gates with Low VDD (N-1)(N6)
• (31)(38) 1178 19.2
• Number of Gates with Normal VDD
• 6144 1178 4966 80.8

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Power Estimation

• Using Dual-Voltages, 1.8V 1.5V
• Power Consumption
• (0.192)(8.45mW) (0.808)(13.63mW)
• 12.64 mW
• 7.3 Power Reduction

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Power Estimation

• Using Dual-Voltages, 1.8V 1.2V
• Power Consumption
• (0.192)(4.85mW) (0.808)(13.63mW)
• 11.9 mW
• 12.4 Power Reduction

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Conclusion

• Pros
• Reduction in power
• Delay is not compromised
• No change in Area
• Dual-power supply is easy to generate using
  potential dividers
• Cons
• The percentage of the circuit that can be fed
  with Low Voltage supply is less
• Requires careful assignment of Low Voltage Supply

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Comments

• Learnt VHDL basics
• Introduction to very useful EDA tools
• Get a feel of VLSI Design
• Appreciation of Low Power Design
• Time Consuming but worth it