Lecture 15 External SRAM

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Lecture 15External SRAM
ECE 448 FPGA and ASIC Design with VHDL
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Required reading

• P. Chu, FPGA Prototyping by VHDL Examples
• Chapter 10, External SRAM

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Block diagram of a typical SRAM
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SRAM Functional Table
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SRAM Simplified Functional Table
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Timing diagram of an address-controlled read
cycle
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Timing diagram of an output_enable-controlled
read cycle
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SRAM Timing Parameters (in ns)
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Timing diagram of write cycle
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SRAM Timing Parameters (in ns)
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Role of a memory controller
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Block diagram of a memory controller
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ASM chart of a safe SRAM controller
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ASM chart of a testing circuit
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ASM chart of an alternativeSRAM controller
design I
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ASM chart of an alternativeSRAM controller
design II
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ASM chart of an alternativeSRAM controller
design III
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Generating a half cycle with DDR