Computer Architecture I: Digital Design

1
Computer Architecture I Digital Design Dr.
Robert D. Kent
Logic Design Medium Scale Integration
and Programmable Logic Devices Part II
2
Review

• At the outset of designing a complex system, such
  as a modern computer or network, it is clear that
  design is extraordinarily difficult and
  computationally challenging when performed at the
  level of fundamental Boolean logic gates.
• For these reasons modern design approaches are
  based on hierarchical, component based methods.
• Leading to simplified, localized component
  design,
• lowering of design costs,
• shifting some aspects of design to the component
  interface (the compatibility problem).
• We now continue our study of MSI circuits to
  better understand this process of MSI design.

3
Goals

• We continue our study of simple, but functional
  Combinational circuits
• we continue constructing a small library of
  useful components
• through study of the solution process using
  Boolean algebra and Boolean calculus
  (simplification, etc.) we better understand the
  meaning of SSI design
• we seek to identify these components for their
  re-use potential
• through our study we will better understand how
  MSI increases the level of abstraction in solving
  problems - SSI design is relatively concrete.

4
Circuit 4 Binary Subtractor
5
Circuit 4 Binary Subtractor

• Before proceeding to design a subtractor circuit,
  consider a few examples of the operation D X -
  Y
• Example 1

• Example 1
• X 0 0 1 1
• Y 0 0 0 1
• D 0 0 1 0

Considered easy because 1-1 0 is easy 1-0
1 is easy 0-0 0 is easy But .....
6
Circuit 4 Binary Subtractor

• Example 2
• This is not straightforward it requires the
  concept of borrowing from the column on the
  left.
• Use a trick add zero! Introduce a borrow
  constant, B. For an L-bit representation, B 2L.

• Example 2
• B 1 0 0 0 0
• X 0 0 1 1
• Y 0 1 0 1
• D 1 1 1 0

This is not a mathematical zero. Rather, it is a
practical zero since we only use the low-order 4
bits.
7
Circuit 4 Binary Subtractor

• Example 2
• This is not straightforward it requires the
  concept of borrowing from the column on the
  left.
• Use a trick add zero! Introduce a borrow
  constant, B. For an L-bit representation, B 2L.

• Example 2
• B 1 0 0 0 0
• X 0 0 1 1
• Y 0 1 0 1
• D 1 1 1 0

Instead of XK YK, we have recast this in the
form BK XK YK. NOTE By borrowing from
the left, each successive borrow digit becomes a
1 until the column which forces the first borrow.
This specific borrow digit has the value 2
(binary 10).
B 0 1 2 0 0
8
Circuit 4 Binary Subtractor

• Example 2
• This is not straightforward it requires the
  concept of borrowing from the column on the
  left.
• Use a trick add zero! Introduce a borrow
  constant, B. For an L-bit representation, B 2L.

Now we note that we have already borrowed from
this column (in the next-to-right column). But
we also had to borrow from the next-to-left
column. Hence, we borrow a 2 from the left,
then borrow 1 from this 2 to the right, the
net result is to add 1 to the current column.
The rest of the subtraction (2-10-0)1 is easy.

• Example 2
• B 1 0 0 0 0
• X 0 0 1 1
• Y 0 1 0 1
• D 1 1 1 0

B 0 1 2 0 0
9
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1

10
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0

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Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0

12
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 0

13
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 0

14
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 1

2
15
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1

16
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1

2
17
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1

18
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1

2
19
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1 1 0 0 1 0

20
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1 1 0 0 1 0 1
  0 1 0 0

21
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1 1 0 0 1 0 1
  0 1 0 0 1 1 0 0 0

22
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1 1 0 0 1 0 1
  0 1 0 0 1 1 0 0 0 1 1 1
  1 1

2
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Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1 1 0 0 1 0 1
  0 1 0 0 1 1 0 0 0 1 1 1
  1 1
• The circuit expressions for the outputs are
  derived

24
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1
  0 1 1 0 0 1 0 1
  0 1 0 0 1 1 0 0 0 1 1 1
  1 1
• The circuit expressions for the outputs are
  derived DK XKYKBK XKYKBK XKYKBK
  XKYKBK

25
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 0 1 1 0
  1 1 0 0 1 0 1 0
  1 0 0 1 1 0 0 0 1 1 1 1
  1
• The circuit expressions for the outputs are
  derived DK XKYKBK XKYKBK XKYKBK
  XKYKBK BK xor XK xor YK

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Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 DK BK xor XK
  xor YK 0 1 1 0 1 1 0
  0 1 0 1 0 1 0 0 1 1 0
  0 0 1 1 1 1 1
• The circuit expressions for the outputs are
  derived

27
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 DK BK xor XK
  xor YK 0 1 1 0 1 1 0
  0 1 0 1 0 1 0 0 1 1 0
  0 0 1 1 1 1 1
• The circuit expressions for the outputs are
  derivedBK1 XKYKBK XKYKBK XKYKBK
  XKYKBK

28
Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 DK BK xor XK
  xor YK 0 1 1 0 1 1 0
  0 1 0 1 0 1 0 0 1 1 0
  0 0 1 1 1 1 1
• The circuit expressions for the outputs are
  derivedBK1 XKYKBK XKYKBK XKYKBK
  XKYKBK XKYK(BK BK) XK(YK YK)BK
  (XK XK)YKBK

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Circuit 4 Binary Subtractor

• We begin the design by constructing a
  3-input/2-output truth tableXK YK BK DK
  BK1 0 0 0 0 0 0 0 1 1 10
  1 0 1 1 DK BK xor XK
  xor YK 0 1 1 0 1 1 0
  0 1 0 1 0 1 0 0
  BK1 XKYK XKBK YKBK 1 1 0 0 0
  1 1 1 1 1
• The circuit expressions for the outputs are
  derivedBK1 XKYKBK XKYKBK XKYKBK
  XKYKBK XKYK(BK BK) XK(YK YK)BK
  (XK XK)YKBK

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Circuit 4 Binary Subtractor

• This leads to the expressions DK BK xor XK
  xor YK BK1 XKYK XKBK YKBK
• These have the logic gate realizations

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Circuit 4 Binary Subtractor

• This leads to the expressions DK BK xor XK
  xor YK BK1 XKYK XKBK YKBK
• These have the logic gate realizations

32
Circuit 4 Binary Subtractor

• This leads to the expressions DK BK xor XK
  xor YK BK1 XKYK XKBK YKBK
• These have the logic gate realizations

33
Circuit 4 Binary Subtractor

• We can now employ the 1-bit Full Subtractor to
  construct a multi-bit subtractor
• we use a FS with B0 0 for the first bit.
• this can be replaced with a specialized
  Half-Subtractor circuit.

34
Circuit 4 Binary Subtractor

• We can now employ the 1-bit Full Subtractor to
  construct a multi-bit subtractor
• we use a FS with B0 0 for the first bit. (This
  can be replaced with a specialized
  Half-Subtractor circuit).

35
Circuit 4 Binary Subtractor

• We can now employ the 1-bit Full Subtractor to
  construct a multi-bit subtractor
• we use a FS with B0 0 for the first bit. This
  can be replaced with a specialized
  Half-Subtractor circuit.

36
Circuit 4 Binary Subtractor

• Note that the Full Adder and Full Subtractor are
  identical, except for a single inverter applied
  to the first input (A or X)

37
Circuit 4 Binary Subtractor

• There are alternative methods to performing
  subtraction, based on 1s and 2s complement
  representations.

38
Circuit 4 Binary Subtractor

• There are alternative methods to performing
  subtraction, based on 1s and 2s complement
  representations.
• Since (X - Y) is the same as (XY1) using 2s
  complement arithmetic, we can use the adder to
  perform subtraction by adding inverters to the Y
  inputs and setting the input carry bit to 1.

39
Circuit 4 Binary Subtractor

• There are alternative methods to performing
  subtraction, based on 1s and 2s complement
  representations.
• Since (X - Y) is the same as (XY1) using 2s
  complement arithmetic, we can use the adder to
  perform subtraction by adding inverters to the Y
  inputs and setting the input carry bit to 1.

40
Circuit 5 Binary Adder/Subtractor
41
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gate

42
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gateA xor 1 A

43
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gateA xor 1 A Proof 0 xor 1 1 0
  1 xor 1 0 1

44
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gateA xor 1 A Proof 0 xor 1 1 0
  1 xor 1 0 1A xor 0 A

45
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gateA xor 1 A Proof 0 xor 1 1 0
  1 xor 1 0 1A xor 0 A Proof 0 xor
  0 0 1 xor 0 1

46
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gateA xor 1 A Proof 0 xor 1 1 0
  1 xor 1 0 1A xor 0 A Proof 0 xor
  0 0 1 xor 0 1
• These properties of the xor gate allow us to
  construct a circuit that can perform either
  addition or subtraction

47
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gateA xor 1 A Proof 0 xor 1 1 0
  1 xor 1 0 1A xor 0 A Proof 0 xor
  0 0 1 xor 0 1
• These properties of the xor gate allow us to
  construct a circuit that can perform either
  addition or subtraction

48
Circuit 5 Binary Adder/Subtractor

• Finally, we note the following facts about the
  xor gateA xor 1 A Proof 0 xor 1 1 0
  1 xor 1 0 1A xor 0 A Proof 0 xor
  0 0 1 xor 0 1
• These properties of the xor gate allow us to
  construct a circuit that can perform either
  addition or subtraction

The input carry bit is used as a toggle to
control the choice of addition or subtraction.
/- /- /- /-
49
Circuit 5 Binary Adder/Subtractor

• Now that it has been demonstrated that
  subtraction can be carried out using addition
  circuits, we may henceforth treat only addition
  cases, without any loss of generality.

/- /- /- /-
50
Circuit 6 Carry Lookahead Adder
51
Circuit 6 Carry Lookahead Adder

• The representation of the Carry-out circuit for
  the full adder is CK1 XK YK CK XK CK YK
  XK YK CK (XK YK)

52
Circuit 6 Carry Lookahead Adder

• The representation of the Carry-out circuit for
  the full adder is CK1 XK YK CK XK CK YK
  XK YK CK (XK YK)
• Define terms gK XK YK and, pK (XK
  YK)
• We may now write CK1 gK CK pK

53
Circuit 6 Carry Lookahead Adder

• The representation of the Carry-out circuit for
  the full adder is CK1 XK YK CK XK CK YK
  XK YK CK (XK YK)
• Define terms gK XK YK and, pK (XK
  YK)
• We may now write CK1 gK CK pK
• Also, recall that the sum bit is generated using
  the expression SK CK xor AK xor BK

54
Circuit 6 Carry Lookahead Adder

• Using the expressions CK1 gK CK pK SK
  CK xor AK xor BK We define the Sigma-block
  circuit

55
Circuit 6 Carry Lookahead Adder

• Using the expressions CK1 gK CK pK SK
  CK xor AK xor BK We define the Sigma-block
  circuit
• This may be abbreviated as the MSI component

56
Circuit 6 Carry Lookahead Adder

• Using the expressions CK1 gK CK pK SK
  CK r AK r BK We define the Sigma-block
  circuit
• This may be abbreviated as the MSI component

Note that both P and G only require evaluation of
one logic gate.
SIG
57
Circuit 6 Carry Lookahead Adder

• These results suggest that the previous
  ripple-adder circuit may be replaced by the
  following circuit, using Sigma-blocks

SIG
SIG
SIG
SIG
58
Circuit 6 Carry Lookahead Adder

• Expanding the carry terms for a 4-bit adder

C1 g0 C0 p0 C2 g1 C1 p1 g1
(g0 C0 p0 )p1 g1 g0 p1 C0 p0 p1 C3
g2 C2 p2 g2 g1 p2 g0 p1 p2 C0 p0
p1 p2 C4 g3 C3 p3 g3 g2 p3 g1
p2 p3 g0 p1 p2 p3 C0 p0 p1 p2 p3
59
Circuit 6 Carry Lookahead Adder

• Expanding the carry terms for a 4-bit adder

Note that all the carry expressions require only
two evaluation stages (one for the and, the other
for the or).
C1 g0 C0 p0 C2 g1 C1 p1 g1
(g0 C0 p0 )p1 g1 g0 p1 C0 p0 p1 C3
g2 C2 p2 g2 g1 p2 g0 p1 p2 C0 p0
p1 p2 C4 g3 C3 p3 g3 g2 p3 g1
p2 p3 g0 p1 p2 p3 C0 p0 p1 p2 p3
60
Circuit 6 Carry Lookahead Adder

• These results can now be used to complete the
  Carry lookahead network portion of the 4-bit
  adder

C0
Carry lookahead network
C4
SIG
SIG
SIG
SIG
61
Circuit 6 Carry Lookahead Adder

• These results can now be used to complete the
  Carry lookahead network portion of the 4-bit
  adder

62
Circuit 6 Carry Lookahead Adder
Now it is clear that evaluation of each carry
requires, at most, 3 logic gates. Thus, each sum
digit requires at most 4 logic gates.

• These results can now be used to complete the
  Carry lookahead network portion of the 4-bit
  adder

63
Circuit 6 Carry Lookahead Adder

• This brings us back to the basic, 4-bit MSI
  Adder/Subtractor, which may now be assumed to be
  optimized with carry lookahead circuits.
• These may be used, in turn, to develop more
  powerful multi-bit adder/subtractors.

64
Circuit 7 Decimal Adder
65
Circuit 7 Decimal Adder

• There are many situations where it is useful to
  employ decimal arithmetic on decimal
  representations (e.g. BCD 8421).
• BCD 0 1 2 7
  8 9 0000, 0001, 0010, , 0111,
  1000, 1001

Remind yourself that BCD uses a 4-bit
representation to store the values of digits
0..9, but this leaves wastage of some bit
patterns (unused patterns).
66
Circuit 7 Decimal Adder

• There are many situations where it is useful to
  employ decimal arithmetic on decimal
  representations (e.g. BCD 8421).
• BCD 0 1 2 7
  8 9 0000, 0001, 0010, , 0111,
  1000, 1001
• To illustrate some of the issues we consider one
  example of decimal addition of single digits,
  leading to a full decimal adder.
• This design will be based on the use of the
  binary adder.

67
Circuit 7 Decimal Adder

• Note that the problem of adding two decimal
  digits together, in general, also requires
  accounting for an input carry and an output
  carry.Minimum Sum Maximum Sum 0 (No
  carry) 1 (Carry) 0 9
  0 9 0 19(No Carry
  out) DECIMAL ARITHMETIC (Carry out)
• Note also that the maximum number of distinct
  sums is 20.

68
Circuit 7 Decimal Adder
Consider the example Carry 1110 999
99 Sum 1998

• Note that the problem of adding two decimal
  digits together, in general, also requires
  accounting for an input carry and an output
  carry.Minimum Sum Maximum Sum 0 (No
  carry) 1 (Carry) 0 9
  0 9 0 19 DECIMAL
  ARITHMETIC (Carry out)
• Note that the maximum number of distinct sums is
  20.

69
Circuit 7 Decimal Adder

• We can obtain the sumsin two stages.

70
Circuit 7 Decimal Adder
Direct sum of decimal digits,ranging from 0 to
1910, represented in 5-bit form with high-order
bit K.

• We can obtain the sumsin two stages.
• First, list all possible outputs from the direct
  sum of the decimaldigits, then ..

71
Circuit 7 Decimal Adder

• We can obtain the sumsin two stages.
• First, list all possible outputs from the direct
  sum of the decimaldigits, then ..
• Beside each sum placethe expected values ofthe
  sum bits and thecarry out bit.

Expected outputs, with sum bits SJ and carry-out
bit C.
72
Circuit 7 Decimal Adder

• The first-stage sumsdivide into two groups
• the first ten sumsproduce the correctfinal sum
  and carrybit patterns

73
Circuit 7 Decimal Adder

• The first-stage sumsdivide into two groups
• the first ten sumsproduce the correctfinal sum
  and carrybit patterns
• the last ten sumsare all incorrect bythe same
  amount,they should have 6 added to them to
  produce the correctfinal bit patterns.

74
Circuit 7 Decimal Adder

• The first-stage sumsdivide into two groups
• the first ten sumsproduce the correctfinal sum
  and carrybit patterns
• the last ten sumsare all incorrect bythe same
  amount,they should have 6 added to them to
  produce the correctfinal bit patterns.

6
6
75
Circuit 7 Decimal Adder

• The condition used to identify and control the
  correction process isexpressed in terms of the
  carry-out bit, CC K P3 P2 P3 P1

76
Circuit 7 Decimal Adder

• The condition used to identify and control the
  correction process isexpressed in terms of the
  carry-out bit, CC K P3 P2 P3 P1
• Thus, if C 0 then nocorrection is applied.

77
Circuit 7 Decimal Adder

• The condition used to identify and control the
  correction process isexpressed in terms of the
  carry-out bit, CC K P3 P2 P3 P1
• Thus, if C 0 then nocorrection is applied.
• If C 1, then 6 is addeddirectly to the initial
  sumbits PJ .

This is referred to as the Excess-64 technique
for BCD addition.
6
6
78
Circuit 7 Decimal Adder

• The condition used to identify and control the
  correction process isexpressed in terms of the
  carry-out bit, CC K P3 P2 P3 P1
• A decimal full-adder circuit follows usinga
  two-stage 4-bit binaryadder MSI circuit and
• Uses the carry bit valuedirectly to generate
  thevalue 610, or 01102.

79
Circuit 7 Decimal Adder

• This MSI circuit is used to form the basis for a
  multi-decade decimal adder.

80
Time out for some Design Philosophy!
81
Time out for some Philosophy!

• In software design and construction the
  programmer/analyst becomes familiar with
  identifying different aspects of the problem in
  terms of abstract models.
• Some of these models are quite concrete
  (bottom-up design) while others are relatively
  more abstract and require gradual expression of
  their detail (top-down design).

82
Time out for some Philosophy!

• Increasingly, modern Software Design is expressed
  in terms of components (functions,
  classes/objects, templates, metaprogramming) and
  focuses on software component re-use.
• One critical problem of software re-use lies in
  the proper, robust, flexible and standards-based
  design of the component interfaces.
• Other issues arise in the contexts of software
  complexity, performance, cost and other factors.

83
Time out for some Philosophy!

• Differential layering of abstraction in design
  also has its place in hardware design.SSI
  Boolean algebra / Simplification / Logic gates
  MSI Interconnection networks / Iterative
  re-use / Components
• These differences have been demonstrated in each
  of the circuits/components that we have
  considered so far.

84
Time out for some Philosophy!

• Differential layering of abstraction in design
  also has its place in hardware design.SSI
  Boolean algebra / Simplification / Logic gates
  MSI Interconnection networks / Iterative
  re-use / Components
• These differences have been demonstrated in each
  of the circuits/components that we have
  considered so far.

85
Circuit 8 Comparator
86
Circuit 8 Comparator

• The comparison of two (binary) numbers is of
  considerable importance.
• if ( A lt B ) then
• while ( A gt B ) do ...

87
Circuit 8 Comparator

• The comparison of two (binary) numbers is of
  considerable importance.
• if ( A lt B ) then
• while ( A gt B ) do ...
• It is possible to design a comparator circuit
  that establishes whether two input binary
  strings, A and B, satisfy the conditions
  A B A gt B A lt
  B

88
Circuit 8 Comparator

• The comparison of two (binary) numbers is of
  considerable importance.
• if ( A lt B ) then
• while ( A gt B ) do ...
• It is possible to design a comparator circuit
  that establishes whether two input binary
  strings, A and B, satisfy the conditions
  A B A gt B A lt
  BThese conditions may be encoded using 3 flag
  bits E 1 G
  1 L 1

89
Circuit 8 Comparator

• One strategy is to perform the comparison
  bit-wise and from right to left.

90
Circuit 8 Comparator

• One strategy is to perform the comparison
  bit-wise and from right to left.
• Express the two bit strings to be compared, A and
  BAN AK AK-1 A1 A0 and BN BK
  BK-1 B1 B0

91
Circuit 8 Comparator

• One strategy is to perform the comparison
  bit-wise and from right to left.
• Express the two bit strings to be compared, A and
  BAN AK AK-1 A1 A0 and BN BK
  BK-1 B1 B0
• Now, restrict attention to the substringsAK
  AK-1 A1 A0 and BK BK-1 B1 B0

92
Circuit 8 Comparator

• We begin with three distinct, possible
  assumptions

93
Circuit 8 Comparator

• We begin with three distinct, possible
  assumptions AK-1 A1 A0 BK-1 B1 B0
  EK-1 1 , GK-1 0 , LK-1 0

94
Circuit 8 Comparator

• We begin with three distinct, possible
  assumptions AK-1 A1 A0 BK-1 B1 B0
  EK-1 1 , GK-1 0 , LK-1 0 AK-1 A1 A0 gt
  BK-1 B1 B0 EK-1 0 , GK-1 1 , LK-1 0

95
Circuit 8 Comparator

• We begin with three distinct, possible
  assumptions AK-1 A1 A0 BK-1 B1 B0
  EK-1 1 , GK-1 0 , LK-1 0 AK-1 A1 A0 gt
  BK-1 B1 B0 EK-1 0 , GK-1 1 , LK-1
  0 AK-1 A1 A0 lt BK-1 B1 B0 EK-1 0 ,
  GK-1 0 , LK-1 1

96
Circuit 8 Comparator

• We begin with three distinct, possible
  assumptions AK-1 A1 A0 BK-1 B1 B0
  EK-1 1 , GK-1 0 , LK-1 0 AK-1 A1 A0 gt
  BK-1 B1 B0 EK-1 0 , GK-1 1 , LK-1
  0 AK-1 A1 A0 lt BK-1 B1 B0 EK-1 0 ,
  GK-1 0 , LK-1 1
• Note that only one of EK-1, GK-1 or LK-1 may have
  value 1 at a time.

97
Circuit 8 Comparator

• We begin with three distinct, possible
  assumptions AK-1 A1 A0 BK-1 B1 B0
  EK-1 1 , GK-1 0 , LK-1 0 AK-1 A1 A0 gt
  BK-1 B1 B0 EK-1 0 , GK-1 1 , LK-1
  0 AK-1 A1 A0 lt BK-1 B1 B0 EK-1 0 ,
  GK-1 0 , LK-1 1
• Note that only one of EK-1, GK-1 or LK-1 may have
  value 1 at a time.
• Our goal is to derive expressions for outputs EK,
  GK and LK based on the inputs AK , BK , EK-1 ,
  GK-1 and LK-1 .

98
Circuit 8 Comparator

• Construct an abbreviated truth-tableAK BK
  EK-1 GK-1 LK-1 EK GK LK 0 0 0 0
  1 0 0 10 0 0 1 0 0
  1 00 0 1 0 0 1 0 00 1
  0 0 1 0 0 10 1 0 1 0
  0 0 10 1 1 0 0 0 0
  11 0 0 0 1 0 1 01 0 0
  1 0 0 1 01 0 1 0 0
  0 1 01 1 0 0 1 0 0 11
  1 0 1 0 0 1 01 1 1 0 0
  1 0 0
• Note that all other (missing) rows are
  represented using dont care output values.

99
Circuit 8 Comparator

• Construct an abbreviated truth-tableAK BK
  EK-1 GK-1 LK-1 EK GK LK 0 0 0 0
  1 0 0 10 0 0 1 0 0
  1 00 0 1 0 0 1 0 00 1
  0 0 1 0 0 10 1 0 1 0
  0 0 10 1 1 0 0 0 0
  11 0 0 0 1 0 1 01 0 0
  1 0 0 1 01 0 1 0 0
  0 1 01 1 0 0 1 0 0 11
  1 0 1 0 0 1 01 1 1 0 0
  1 0 0
• Note that all other (missing) rows are
  represented using dont care output values.

Condition is not altered when AK BK
Condition is not altered when AK BK
100
Circuit 8 Comparator

• Construct an abbreviated truth-tableAK BK
  EK-1 GK-1 LK-1 EK GK LK 0 0 0 0
  1 0 0 10 0 0 1 0 0
  1 00 0 1 0 0 1 0 00 1
  0 0 1 0 0 10 1 0 1 0
  0 0 10 1 1 0 0 0 0
  11 0 0 0 1 0 1 01 0 0
  1 0 0 1 01 0 1 0 0
  0 1 01 1 0 0 1 0 0 11
  1 0 1 0 0 1 01 1 1 0 0
  1 0 0
• Note that all other (missing) rows are
  represented using dont care output values.

Condition LK 1 always applies when AK lt BK
101
Circuit 8 Comparator

• Construct an abbreviated truth-tableAK BK
  EK-1 GK-1 LK-1 EK GK LK 0 0 0 0
  1 0 0 10 0 0 1 0 0
  1 00 0 1 0 0 1 0 00 1
  0 0 1 0 0 10 1 0 1 0
  0 0 10 1 1 0 0 0 0
  11 0 0 0 1 0 1 01 0 0
  1 0 0 1 01 0 1 0 0
  0 1 01 1 0 0 1 0 0 11
  1 0 1 0 0 1 01 1 1 0 0
  1 0 0
• Note that all other (missing) rows are
  represented using dont care output values.

Condition GK 1 always applies when AK gt BK
102
Circuit 8 Comparator

• This leads to Boolean expressions for the outputs
  (using dont cares)AK BK EK-1 GK-1 LK-1
  EK GK LK 0 0 0 0 1 0 0
  10 0 0 1 0 0 1 00 0 1
  0 0 1 0 00 1 0 0 1
  0 0 10 1 0 1 0 0 0 10
  1 1 0 0 0 0 11 0 0 0 1
  0 1 01 0 0 1 0 0 1
  01 0 1 0 0 0 1 01 1 0
  0 1 0 0 11 1 0 1 0
  0 1 01 1 1 0 0 1 0 0

103
Circuit 8 Comparator

• The 1-bit comparator circuit is expressed

104
Circuit 8 Comparator

• The 1- bit comparator circuit is expressed in MSI
  form

105
Circuit 8 Comparator

• The 1- bit comparator circuit is expressed in MSI
  form

106
Summary - Part II

• We continue to study logic design in the contexts
  of Small Scale Integration (SSI) and Medium Scale
  Integration (MSI) of gate devices and
  programmable logic devices (PLD).
• We have studied the design of a number of
  specific, practical functional circuits with a
  view to re-using those circuits as components in
  MSI design. Adders
  Subtractors Comparator
• We note the differing design approaches, or
  emphases, effected by differential layering of
  abstraction. (The same design issue arises in
  the context of software engineering as well.)
  SSI Boolean algebra / Simplification /
  Logic gates MSI Interconnection
  networks / Iterative re-use / Components