Diapositive 1

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A 0.13um CMOS Rad-hard proven technology with
associated mixed mode circuit design approaches
for space applications
Laurent Dugoujon (1), Constantin Papadas (2) and
Bill Sinnis (2) 1) ST Microelectronics, 12 rue
Jules Horowitz, B.P. 217, 38019 Grenoble Cedex,
France 2) Integrated Systems Development S.A.,
Atrina Center, Building B, 32 Kifisias Avenue,
15125 Marousi, Greece.
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INTRODUCTION

• New Telecommunications Satellites must offer
• High data throughput
• Uninterrupted Service
• High Reliability
• Competitive costs

- The usage of Deep-Sub-Micron technology is now
mandatory to keep-up with US manufacturers -
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KEY FUNCTIONS

• Some functions are  key  to succes
• Broadband Analog-Digital Converters ADC DAC
• High Speed Serial Links
• Digital Processing ASICs

- For these key components, only modern
technology nodes (lt0.25um) can fulfill the
specifications -
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TECHNOLOGY / FUNCTIONS
0.25um 0.13um 0.09um
DC-1GHz Analog functions 1-2GHz Mixed Analog Digital 1-4GHz HSSL
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RH at PROCESS LEVEL
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0.13µm Technology Platforms Digital/Analog/RF
convergence
HCMOS9 Core Process 4 or 6 Cu Dual Damascene
Metal levels 0.41µm pitch metallization, Low k
dielectric
HCMOS9DRAM 0. 39/ 0.53µm²
HCMOS9i
HCMOS9 A
HCMOS9 SOI
BICMOS9
HCMOS9 SiGe
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HCMOS9 Device list

• CAPACITORS
• 2 fF/µm² MIM capacitor (option)
• NPoly/NWell capacitor (GO250A)
• PPoly/PWell capacitor (GO250A)
• Interdigited Metal fringe capacitor (MOM)
• Intermetal capacitor (MEM)

• MOSFETs
• 1.2V HS 0.13µm CMOS (GO1 20A)
• 1.2V LL 0.13µm CMOS (GO1 20A)
• 2.5V CMOS (GO2 50A)
• 2.5V HS CMOS (GO2 50A) (option)
• DRIFT N P MOS transistors (GO250A)
• NMOS SRAM (option)

• JUNCTION DIODES
• N/Pwell
• P /Nwell

• RESISTORS
• Silicided N Poly 10 Ohm/sq
• Unsilicided p Active 135 Ohm/sq
• Unsilicided P Poly 320 Ohm/sq
• Hipo 1KOhm/sq (option)
• Unsilicided N Poly 110 Ohm/sq

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ST 130 90nm SRAMs are invulnerable to thermals

• Thermal neutrons highly interact with Boron10
• Highest concentration of Bo10 in todays IC
• borophosphosilicate glass (BPSG) film not used
  in ST technologies
• Test on 130nm ST SRAMs at ILB, Paris no SEU
  with a fluence gt1011n/cm2
• Test on a 90nm SRAMs at TRIUMF, Vancouver no
  SEU variations with without Cadnium shielding

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TID characterizations for 130nm MOSFETs
(r)SRAMs

• Linear transistors 130nm (thin oxide) _at_ 30 MradSi
  - Tests performed by CERN
• Threshold voltage shift lt 10 mV negligible
• Subthreshold swing variations negligible
• Transconductance degradation of less than 10
• Linear transistors 130nm (thick oxide) _at_ 30
  MradSi - Tests performed by CERN
• Threshold voltage shift lt 35 mV negligible
• Transconductance degradation of less than 10
• Two 130nm 1Mb SRAMs, standard and rSRAM tested at
  BNL _at_ 1 MradSi
• No bit error detected for each memory cut at
  initial and after each exposure step (0, 100, 500
  and 1000Krads(Si))
• Full functionality verified for the 2 cuts after
  being exposed to 1Mrad(Si).

These experimental results confirm the strong
robustness of ST 130nm MOSFETS, SRAM and robust
SRAMs CERN test report specifications should
be met in terms of radiation requirements WITHOUT
using enclosed transistors (with obvious
benefits)
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Responses to HI of 130nm regular robust
rSRAMs Experiments performed at the BNL, NY,
01/2004
Std SRAM
rSRAM ref.
The rSRAM has both a lower LETth (x10)
X-section at sat. (/3) than the regular SRAM No
SEL recorded up to 80 MeV/cm2.mg for all tested
SRAMs
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RH at LIBRARY LEVEL
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RHBD Library Level
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RHBD Library Level

• Or
• Trench capacitors
• Drain degeneration by drain contact distance
• Silicide protect
• Salicide protect

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RHBD Library Level
Redundant Latch
Layout
Standard (6 xtors)
Redundant (14 xtors)
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RHBD Library Level
Triple Voting Scheme
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RH at DESIGN LEVEL
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RHBD Architecture Level
ECC
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rSRAM validation Testchip in 130 nm

• Content
• SRAM Standard 1Mb
• memcell 2.5 µm2
• SRAM Standard 1Mb
• memcell 2.5 µm2 with Triple Well
• rSRAM 1Mb
• robust memcell 2.5 µm2
• rSRAM 1Mb
• robust memcell 2.5 µm2 - ver. 2
• (lower capacitor value)
• 50x164Kb
• robust memcell 2.5 µm2
• Package
• PBGA 27x27 27616

1Mb SRAM
1Mb SRAM
1Mb rSRAM
1Mb rSRAM
scribes
PLL, BIST, Laser Fuses
Chip micrograph
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Relative perf between a standard, robust and ECC
SRAM 130nm Single-Port SRAM - 32kx32 HCMOS9GP-LL,
typical corner, 1V2, room temp. 90nm Single-Port
SRAM - 8kx32 CMOS90-GP, typical corner, 1V, room
temp.
SRAM Specifications SRAM Specifications rSRAM ? in rSRAM ? in SRAM ECC1,2 ? in
tcycle (ns) 4.2 1.50 5 1 0
taa (ns) 3.7 0.95 5 1 one cycle later
area (mm2) 3.6 0.4 0 0 25
power (µW/MHz) 160 50 20 5 40
leakage (uA, WC) 1016 400 0 0 20-25
Process Standard Standard eDRAM option eDRAM option Standard
Wafer cost 1 1 1.10 1.10 1
Die cost (10Mb/ 32-bit word) 1 1 1.10 1.10 gt1.25
Note1 pipeline architecture, Note2 penalty
induced by the additional parity bits ( 7 bits
for a 32 bit-word ) and combinatonial logic (XOR
stage)
rSRAM offers lower die cost than ECC with a
similar robustness
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Alpha neutron responses of the 130nm
rSRAM Experiments performed at Los Alamos and
Crolles, 2003
Alpha accelerated results _at_ 1.2V
Neutron accelerated results _at_ 1.2V
Nominal Conditions (1.2 V, room temp) SRAM standard cell area2.5 µm2 rSRAM cell area2.5 µm2
Alpha fail rate 37,000 fails/min 0 after 23h, Th232
Neutron fail rate 1,195 fails after 6 h 8 fails after 6 h
Total SER FIT/Mb 1475 6 6 4
ST rSRAM provides a robustness enhancement by
250 SER lt 10 FIT/Mb _at_ 1.2 V full immunity _at_
1.32 V
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RHBD Library Mapping (synthesis)
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Robust Designs PLL and Sense Amplifier
PLL Technology 0.13um Locking Frequency
620MHz CtoC Jitter 17ps Power Consumption 340mW
Sense Amplifier Technology 0.13um Bandwidth
4GHz Gain 12db Power Consumption 15mW
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Robust Designs 64x1bit ADC
64x1bit-ADC Technology 0.13um Sampling
Frequency 3GHz Power Consumption 500mW
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Robust Designs 10bit DAC
10bit-DAC Technology 0.13um Topology Current
Steering Sampling Frequency 15MHz Signal
bandwidth2.5MHz ENOB 8.73bits Imax1.4mA Noise
/- 2LSB
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Robust Designs 10bit ADC
10bit-ADC Technology 0.13um Topology
Interleaved SAR Sampling Frequency
1.3GHz Consumption 400mW ENOB in test Noise
in test
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CONCLUSION

• It is the CONJUNCTION of 3 main levels of efforts
  which can maximize the Radiations performances
• Intrinsic good choices at Si process level
  (materials,...)
• usage of validated mitigation techniques
  (libraries, options,...)
• design for Rad-hard (architecture,
  registers,...)
• We are able to manage all these levels with
  additional know-how from space industry trough
  contractual projects