Introduction to PCI System Architecture

1
Introduction to PCI System Architecture
2
Contents

• Introduction to PCI System
• PCI Bus Arbitration
• The PCI Commands
• The Read and Write Transfers
• Premature Transaction Termination
• Shared Resource Acquisition
• Error Detection and Handling
• Configuration Related Issues
• Interrupt Related Issues
• PCI Cache Supports
• Expansion ROMs

3

• Introduction to PCI System

4
Direct-Connect Approach(VESA)
Main memory
CPU
Cache
Local Bus
Memory Bus
Expansion Bridge
Local Bus Device
Local Bus Design Constraint 1. Redesign is
necessary for next generation processor. 2.
Only one local device is permitted. 3.
Design of local bus inter -face is
difficult. 4. Transfer with one device is
not permitted while the local bus is
involved in a transfer with another
device.
Expansion Bus
X-Bus Buffer
Expansion Connectors
X-Bus
I/O Device
I/O Device
I/O Device
5
Buffered Approach(VESA)
CPU
Cache
Local Bus
Memory Bus
Expansion Bridge
Bus Buffer
Buffered Local Bus
Expansion Bus
X-Bus Buffer
I/O Device
I/O Device
I/O Device
X-Bus
A maximum of three local bus devices can be
placed on the buffered local bus.
I/O Device
I/O Device
I/O Device
6
Workstation Approach(PCI)
Video Memory
Main Memory
CPU
Memory Bus
CPU Local Bus
Host/PCI Cache/Bridge
Audio Peripheral
Motion Video Peripheral
PCI Bus
Graphics Adapter
Expansion Bus Bridge
SCSI Host Bus Adapter
LAN Adapter
LAN
Video Frame Buffer
Disk
SCSI BUS
Expansion Bus
Tape
Bus Master
Memory Slave
I/O Slave
CD ROM
7
Transfer Rate Comparison
Bus Bus Frequency Transfer Transfer
Rate ISA 8.33 MHz 2 byte / 2 clock 8.33
MB/s EISA 8.33 MHz 4 byte / 1 clock 33
MB/s ( Burst Mode) VESA 33 MHz 4 byte /
1 clock 132 MB/s ( Read, Burst ) 4
byte / 2 clock 66 MB/s ( Write, Burst
) PCI 33 MHz 4 byte / 1 clock 132
MB/s 8 byte / 1 clock 264 MB/s 66
MHz 4 byte / 1 clock 264 MB/s 8 byte
/ 1 clock 528 MB/s ( Burst Mode )
8

• PCI Peripheral Component Interconnect
• Major PCI Revision 2.1 Features
• ? Processor Independence
• ? Support for up to 256 PCI functions per
  PCI bus
• ? Low power consumption ( Draw as little
  current as possible )
• ? Burst used for all read and write
  transfers
• ? Supports 66 MHz operation, 64bit bus
  width
• ? Fast access ( 60ns at bus speed 33 MHz )
• ? Concurrent bus operation
• ? Bus master support
• ? Hidden bus arbitration
• ? Low pin count ( Initiator49pins,
  Target47 pins )
• ? Transaction integrity check( Parity
  check)
• ? Three address spaces ( Memory, I/O,
  Configuration )
• ? Auto configuration( Configuration
  register )
• ? Software Transparency

9
PCI-Compliant Device Signals
For Slave only
For Master only
Required Signals
Optional Signals
AD3100
AD6332
Address/Data and Command
64-bit Extension
C/BE30
C/BE74
PCI COMPLIANT DEVICE
PAR
PAR64
REQ64
FRAM
ACK64
TRDY
LOCK
Atomic Access
Interface Control
IRDY
INTA
STOP
INTB
DEVSEL
Interrupt Request
INTC
IDSEL
INTD
Error Reporting
PERR
CLKRUN
Clock Control
SERR
SBO
Snoop Result
REQ
SDON
Arbitration
GNT
TDI
TDO
CLK
TCK
JTAG
System
RST
TMS
TRST
10

• PCI Bus Arbitration

11
Initiator/ Target

• Initiator ( Master ) The device that initiates
  a transfer

• Target ( Slave ) The device that currently
  addressed by the initiator for
• the purpose of performing a data transfer

PCI Arbiter
GNT0
GNT1
GNT2
GNT3
REQ0
REQ1
REQ2
REQ3
PCI Device
PCI Device
PCI Device
PCI Device
MASTER
Address, Command/ Data, Byte Enables/ Parity
PCI Device
DRAM
Bridge
SLAVE
SLAVE
SLAVE
12
PCI Bus Arbitration Algorithm
First Group
Master A
Second Group
Master B
Master Z
A B X A B Y A B
Z A B X

• Fairness ( fixed, rotational )
• Bus Parking( on specified master, on last master
  that acquired the bus )
• Hidden Bus Arbitration( REQ, GNT)
• LT ( Latency Timer ) The minimum amount of time
  that the bus master is
• 
  permitted to retain ownership of the bus

13
Example of PCI Bus Arbitration Between Two
Masters
( Master B has higher priority than Master A)
1
2
3
4
5
6
8
9
10
11
12
7
CLK
REQA
( Master A -gt Arbiter )
REQB
( Master B -gt Arbiter )
GNTA
( Arbiter -gt Master A )
GNTB
( Arbiter -gt Master B )
LT not expired
FRAME
( Master -gt Target )
IRDY
( Master -gt Target )
TRDY
( Target -gt Master )
AD
ADDRESS
ADDRESS
ADDRESS
DATA
DATA
DATA
DATA
DATA
( Master lt-gt Target )
A
B
A
14
Arbitration for Fast Back-To-Back Accesses
1
2
3
4
5
6
8
7
CLK
REQ-
GNT
FRAME
AD
ADDRESS
DATA
ADDRESS
DATA
IRDY
TRDY
DEVSEL
15
Delayed Transaction

• Delayed Transaction

Request Phase
Target latches the request and issues retry
Transaction completes on the target bus
Completion Phase
Target cannot respond within 16 clocks
MTXC
Master
1. Address, Command, Byte Enables latched by
PIIX4 2. Retry issued to MTXC ( Request Phase )
PIIX4
Target
3. Requested data fetched in buffer ( Completion
Phase )
4. Master Retries the transaction with the
same address, command, data
ISA Device
OR no Retry within 215 clocks Discard the
data
16
Commands That can Use Delayed Transactions

• Interrupt Acknowledge

• I/O Read

• I/O Write
• Memory Read
• Memory Read Line
• Memory Read Multiple
• Configuration Read
• Configuration Write

17

• The PCI Commands

18
PCI Command Types C/BE30 is used to indicate
the command or transaction type during the
address phase
C/BE30 Command Type 0000
Interrupt Acknowledge 0001
Special Cycle 0010
I/O
Read 0011 I/O Write 0100 Reserved 0101 Reser
ved 0110 Memory Read 0111 Memory
Write 1000 Reserved 1001 Reserved 1010 Conf
iguration Read 1011 Configuration
Write 1100 Memory Read Multiple 1101 Dual
Address Cycle 1110 Memory Read Line 1111
Memory Write and Invalidate
19
PCI Interrupt Acknowledge Transaction
1
2
3
4
5
CLK
FRAME
( Host Bridge -gt INT Controller )
AD
VECTOR
Stable Pattern
( Host Bridge lt -gt INT Controller )
C/BE
Byte Enables
INT ACK CMD
( Host Bridge -gt INT Controller )
IRDY
TRDY
DEVSEL
( INT Controller-gt Host Bridge )
GNT
20
The Special Cycle Transaction( Halt / Shut
Down) Terminated with Master Abort
1
2
3
4
5
6
8
7
CLK

• For an initiator to
• broad- cast a message
• to one or more targets.
• Message type
• on AD150
• Message-dependent
• data field on AD3116
• Byte Enable on
• C/BE30

FRAME
AD310
Stable Pattern
Message
C/BE30
Special Cmd
Byte Enables
IRDY
TRDY
DEVSEL
GNT
7 clocks
21

• The Read and Write Transfers

22
Read Transaction ( 33.33 Mb/s )
CLK
1
2
3
4
5
6
7
8
9
FRAME
Wait state for bus ownership
AD
ADDRESS
DATA-1
DATA-2
DATA-3
C/BE
BUS CMD
BYTE ENABLES
BYTE ENABLES
BYTE ENABLES
IRDY
One more clock before initiator ready to receive
data
Avoid bus contention
TRDY
Some time is needed for fetching data
DEVSEL
DATA PHASE
DATA PHASE
DATA PHASE
ADDRESS PHASE
23
Optimized Read Transaction ( 132 Mb/s)
1
2
3
4
5
6
8
7
CLK
Burst Transfer 1. If target memory is
cacheable. 2. If target memory is
prefetchable
FRAME
AD
Address
Data1
Data2
Data3
C/BE
Byte Enables
Byte Enables
BUS CMD
Byte Enables
IRDY
TRDY
DEVSEL
GNT
24
Write Transaction ( 44.44 Mb/s )
CLK
1
2
3
4
5
6
7
8
9
FRAME
AD
ADDRESS
DATA-1
DATA-2
DATA-3
C/BE
BUS CMD
BYTE ENABLES
Byte EN
Byte EN
IRDY
TRDY
DEVSEL
25
Optimized Write Transaction ( 132 Mb/s)
1
2
3
4
5
6
8
7
CLK
FRAME
AD
Address
Data1
Data2
Data3
C/BE
Byte Enables
Byte Enables
Byte Enables
BUS CMD
IRDY
TRDY
DEVSEL
GNT
26
Addressing

• Addressing Sequence During Memory Burst
• ? Linear ( or Sequential ) address mode
• ? Cache Line wrap mode

AD1 AD0 Addressing Sequence 0 0
Linear 0 1
Reserved 1 0
Cacheline wrap 1 1
Reserved

• PCI I/O Addressing
• ? AD312 Target DW of I/O space
• ? AD10 The Least-significant byte
  within the DW that the
• initiator wishes to transfer with ( 00
  byte 0, 01 byte 1 )

27

• 64 bit PCI Extension
• REQ64, ACK64, PAR64,
• AD6432, C/BE74

28
64-bit Read Request with 64-bit Transfer
CLK
1
2
3
4
5
6
7
8
9
FRAME
REQ64
ADDRESS
DATA-1
DATA-3
DATA-5
AD3100
DATA-2
DATA-4
DATA-6
AD6332
BE s
C/BE30
BUS CMD
BE s
C/BE74
IRDY
TRDY
DEVSEL
ACK64
29
64-bit Write Request with 32-bit Transfer
CLK
1
2
3
4
5
6
7
8
9
FRAME
REQ64
ADDRESS
DATA-1
DATA-3
AD3100
DATA-2
DATA-2
AD6332
BUS CMD
BE s-1
C/BE30
BE s-2
BE s-3
C/BE74
BE s-2
IRDY
TRDY
DEVSEL
ACK64
30
64-bit Dual Address Read Cycle
CLK
1
2
3
4
5
6
7
8
FRAME
LO-ADDR
HI-ADDR
DATA-1
DATA-3
AD3100
DUAL AD
BE 30
C/BE30
BUS CMD
AD6332
HI-ADDR
DATA-2
DATA-4
C/BE74
BUS CMD
BE 74
IRDY
TRDY
DEVSEL
REQ64
ACK64
31

• Premature Transaction Termination

32
Master Initiated Termination

• Reasons

• Transaction completed normally ( Not premature
  transaction termination )
• Initiator been preempted ( GNT removed )
• ? Preemption during timeslice by another bus
  master
• ? Timeslice expiration followed by
  preemption
• Master abort
• ? No target respond to the address ( DEVSEL
  not asserted)
• ? No device resides at the address
• ? Special cycle
• ? Configuration accessing a
  non-existent target

33
Preemption Example
1
2
3
4
5
6
7
CLK
Preempted
GNT
FRAME
Internal LT time out sensed
IRDY
TRDY
CLK
Timer Expiration Example
Preempted
GNT
FRAME
Time out sensed
IRDY
TRDY
34
Example of Master-abort on Single-Data Phase
Transaction
1
2
3
4
5
6
8
7
CLK
FRAME
IRDY
TRDY
Fast
Medium
Slow
Bridge
DEVSEL
Master Abort Target doesnt claim transaction
35

• Target Initiated Termination( STOP )
• Disconnect

• Reasons

• Target slow to complete a data phase which is
  neither the first nor
• the final data phase ( more than 8 PCI
  clocks )
• Targets dont support burst mode
• Memory target doesnt understand address
  sequence
• Transfer cross over targets address boundary
• Burst memory transfer crosses cache line boundary

• Retry

( if the target cannot permit any data to be
transferred )

• Reasons

• Target very slow to complete first data phase (
  Greater than 16 PCI clocks )
• Snoop hit on modified cache line
• Resource busy
• Memory target locked

36

• Target Abort

( if the target detects fatal error )

• Reasons

• Broken Target
• I/O addressing error
• Address phase parity error
• Master abort on other side of PCI-to-PCI bridge

37
Type A Disconnect
Type B Disconnect
Know in advance that the next data transfer takes
more than 8 PCI clock
1
2
3
4
1
2
3
4
CLK
CLK
FRAME
FRAME
IRDY
IRDY
TRDY
TRDY
STOP
STOP
DEVSEL
DEVSEL
Data Transfer
Data Transfer
TRDY asserted, STOP asserted, DEVSEL
asserted, IRDY deasserted
TRDY asserted, STOP asserted, DEVSEL
asserted, IRDY asserted
38
Type C Disconnect with IRDY Asserted
Type C Disconnect without IRDY Asserted
Current data transfer takes more than 8 PCI clock
1
2
3
4
1
2
3
4
CLK
CLK
FRAME
FRAME
IRDY
IRDY
TRDY
TRDY
STOP
STOP
DEVSEL
DEVSEL
Data Transfer
TRDY deasserted, STOP asserted DEVSEL asserted
Data Transfer
39
Retry Received With IRDY Asserted
Retry Received Without IRDY Asserted
1
2
3
4
1
2
3
4
CLK
CLK
FRAME
FRAME
IRDY
IRDY
TRDY
TRDY
STOP
STOP
DEVSEL
DEVSEL
TRDY deasserted, STOP asserted DEVSEL asserted
No Data Transfer
No Data Transfer
Occurs in the first data phase
40
Target Abort Example
1
2
3
4
CLK
FRAME

• Masters response to target abort
• Generates an interrupt to alert is related
• device to check its status.
• Generates SERR

IRDY
TRDY
STOP
DEVSEL
TRDY deasserted, STOP asserted DEVSEL
deasserted
41

• Shared Resource Acquisition

42
Shared Resource Acquisition

• LOCK
• ? Usage Perform read/modify/write of a
  memory
• semaphore as an atomic series to avoid
  
• Synchronization Problem.
• ? Solutions
• Bus LOCK Permissible but not
  preferred
• Resource LOCK Preferred

43
Starting an Exclusive Access ( Establishing LOCK)
1
2
3
4
5
CLK
FRAME
( Master -gt Target )
LOCK
( Master -gt Target )
AD
ADDRESS
DATA
( Master lt -gt Target )
IRDY
( Master -gt Target )
TRDY
( Target -gt Master )
DEVSEL
( Target -gt Master )
GNT
( Arbiter -gt Target )

• LOCK Mechanism Availability
• ? Do not assert REQ if LOCK is currently
  asserted.
• ? If FRAME and LOCK are deasserted,
  assert its REQ.
• ? The master continue to monitor LOCK while
  waiting for GNT.
• If LOCK is sampled asserted, the
  master deasserted its REQ.
• ? When the master samples bus idle ( FRAME
  IRDY deasserted)
• and LOCK deasserted, it has acquisition
  of the bus and of the
• LOCK.

44
Accessing a Locked Agent Retry
1
2
3
4
5
CLK
FRAME
(driven low by master holding lock)
LOCK
ADDRESS
DATA
AD
IRDY
TRDY
STOP
DEVSEL
Retry
GNT
45
Continuing Completing an Exclusive Access
1
2
3
4
5
CLK
FRAME
Release
LOCK
Continue
ADDRESS
DATA
AD
IRDY
TRDY
DEVSEL
GNT
46

• Error Detection and Handling

• When Parity Error occurs
• Configuration status register
  DETECTED PARITY ERROR
• Configuration command register PARITY
  ERROR RESPONSE
• Assert PERR

• Devices excluded from PERR Requirement
• Chipsets
• Devices that dont deal with
  OS/Application program or data

47
Parity on Read Transaction
1
2
3
4
5
6
8
7
9
CLK
FRAME
AD
1st Data
2nd Data
Address
3rd Data
C/BE
2nd Byte Enables
3rd Byte Enables
1st Byte Enables
BUS CMD
PAR
Add phase parity
1st Data parity
2nd Data parity
3rd Data Parity
3rd phase PERR
earliest
latest
PERR
1st phase PERR
2nd phase PERR
IRDY
TRDY
DEVSEL
48
Parity on Write Transaction
1
2
3
4
5
6
8
7
9
CLK
FRAME
AD
1st Data
2nd Data
Address
3rd Data
C/BE
2nd Byte Enables
1st Byte Enables
BUS CMD
3rd Byte Enables
PAR
Add phase parity
1st Data parity
2nd Data parity
3rd Data Parity
3rd phase PERR
earliest
latest
PERR
1st phase PERR
2nd phase PERR
IRDY
TRDY
DEVSEL
49

• Configuration Related Issues

50
Configuration Address Space Format
Byte Number
0
1
2
3
Double Word Number
00
Configuration Header Space
15
16
Device Specific Configuration Registers
63
51
Configuration Registers
Type 0 Configuration Space Header
0
15
16
31
Required configuration registers
00h
Device ID
Vendor ID
Command
04h
Status
08h
Revision ID
Class Code
Cache Line Size
Latency Timer
0Ch
BIST
Header Type
10h
Base Address Registers
24h
28h
Cardbus CIS Pointer
2Ch
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
30h
34h
Reserved
38h
Reserved
3Ch
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
52

• Command Register Bit Assignment

5
3
2
1
0
6
7
8
9
10
4
15
Reserved
Fast Back-to-Back Enable
SERR Enable
Wait Cycle Control
Parity Error Response
Palette Snoop Enable
Memory Write and Invalidate Enable
Special Cycle Monitoring
Enable Mastering
Memory Access Enable
I/O Access Enable

• Status Register

5
0
6
7
8
9
4
15
14
13
12
11
10
Reserved
66MHz-Capable
UDF Supported
Fast Back-to-Back Enable
Data Parity Reported
DEVSEL Timing
Signaled Target Abort
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
53

• Class Code Register

o
7
8
15
16
23
Class Code
Sub-Class Code
Prog I/F
Device specific programming interface
Basic function
More specific device subclass
Eg. 06h
01h 00h
Bridge device
PCI/ISA bridge

• Header Type Register

0
6
7
Header Type
Configuration Header Format
0 single function device 1 multi function
device
54

• BIST Register

7 6 5 4 3
0
Completion Code
Reserved
Start BIST
BIST Capable

• Memory Base Address Register

4
3
2
1
0
31
0
Base Address
Prefetchable
Type
Memory space indicator
Bits 2-1 00
Base register is 32 bits wide and can be mapped
anywhere in the 32-bit memory space.
01 Base register is 32 bits wide must
be mapped below 1M in memory space.
10 Base register is 64 bits wide and can
be mapped anywhere in the 64-bit memory space.
11 Reserved Bit
3 set 1 if prefetchable, set 0 otherwise
55

• I/O Base Address Register

2
1
0
31
1
Base Address
Reserved
I/O space indicator

• Expansion ROM Register

0
1
10
11
31
Expansion ROM Base Address (Upper 21 bits)
Reserved
Address decode enable
56
Configuration Transactions

• Usage Access PCI configuration registers
• A PCI device or host/PCI bridge
  require 64 doubleword of config. register
• Each PCI function requires 64
  doubleword of config. register
• Transaction type
• 1. Type 0 configuration read or write
  transaction
• 2. Type 1 configuration read or write
  transaction
• 3. Memory mapped configuration mechanism (
  PowerPC )
• Configuration mechanism
• 1. Mechanism 1 ( Preferred)
• 2. Mechanism 2

57
System Memory
Peer Host/PCI Bridges
Processor
Memory controller
Host Bus
Bridge A
Bridge B
PCI Bus 0
PCI Bus 4
Expansion Bridge
Bridge D
Bridge E
PCI Device
PCI Bus 0
PCI Device
Bridge C
PCI Bus 0
PCI bus 1
PCI bus 3
Expansion bus
PCI bus5
Bridge C
PCI bus 2
58
Type 0 Configuration Transaction

• Two 32 bit I/O ports are utilized at I/O
  address

CONFIG_ADDRESS PORT 0CF8 h - 0CFB
h CONFIG_DATA PORT 0CFC h - 0CFF h

• Configuration Address Register at 0CF8h

31 30 24 23 16 15
11 10 8 7 2 1 0
DW Number
Device Number
Bus Number
Function Number
0
0
Reserved
1 Enable Configuration space mapping
0CF8h
0CF9h
0CFAh
0CFBh

• Contents of the AD bus during address phase

31 30
11 10 8 7 2
1 0
DW Number
Function Number
0
0
Reserved
0CF8h
0CF9h
0CFAh
0CFBh
59
Implementation of IDSEL
31 30 24 23 16 15
11 10 8 7 2 1 0
DW Number
Device Number
Bus Number
Function Number
0
0
Reserved
Decoder
Device Number
16 15 14 . 1 0
..
31 30 16
15 11 10 8 7 2
1 0
DW Number
..
Function Number
0
0
IDSEL PCI Slot 1
IDSEL PCI Slot 2
IDSEL PCI Slot 3
IDSEL PCI Slot 4
....
60
Type 0 Configuration Read Access
1
2
3
4
5
6
8
7
9
CLK
FRAME
AD
Address
Data
C/BE
Config Read CMD
Byte Enables
IRDY
TRDY
IDSEL
GNT
61
START
Configuration Mechanism 1
Pass PCI-to-PCI bridge
Processor write to config. address reg. at I/O
port 0CF8
Target bus in the range
Host/PCI bridge
YES
Bus num the same
YES
Bus num the same
NO
NO
Type 0 configuration read or write at config.
data port 0CFC
Type 0 configuration read or write at config.
data port 0CFC
Type 1 config. transaction
Type 1 config. transaction
62

• Interrupt Related Issues

63

• Value to be Hardwired into Interrupt Pin Register

• Interrupt Line Register Values

64
Interrupt Design
Programmable Interrupt router
INTA
INTAINTB
Slave 8259
INTA INTB INTC INTD
INTA
IRQ8-15
INTA INTB INTC INTD
Master 8259
INTA
INTAINTB
IRQ0-7
INTA
65
Interrupt Chaining
Device
8259
Entry 1
ISR 1
IRQ 1
INT A
INT B
IRQ 2
Entry 2
ISR 2
If INT A and INT B both routed to IRQ1
ISR 2 with Entry 1 embedded
INT B
Entry 2
IRQ 1
66

• PCI Cache Support

67

• Snoop
• SDONE snoop done
• SBO snoop backoff. ( HITM when assert.)
• The non-cacheable transaction is regardless of
  SDONE and SBO.
• Write Through only use SDONE
• Memory Target Interpretation of Snoop Result
  Signal from Bridge

SDONE SBO Description
0 X
Standby 1 1
Clean snoop 1 0
Hit on a modified line
68
Wait States Inserted Until Snoop Completes
CLK
1
2
3
4
5
6
FRAME
ADDRESS
DATA
AD
IRDY
TRDY
SDONE
SBO
69
Hit to a Modified Line Followed by the Writeback
CLK
1
2
3
4
5
6
B
C
A
FRAME
writeback transaction
ADDRESS
DATA-1
ADDRESS
DATA-1
DATA-2
AD
IRDY
TRDY
DEVSEL
STOP
SDONE
SBO
HITM
HITM
HITM
HITM
STANDBY
STANDBY
CLEAN
70

• Expansion ROMs

71

• device-specific power-on self-test code
• device-specific initialization code
• device-specific interrupt routine
• device-specific BIOS routine
• device-specific code to be executed during the
  system boot process

ROM Detection
Check if Expansion ROM base address register exist
Read if the first two locations on base address
register contain 55AAh
yes
yes
ROM exist
Code image copied to system DRAM Execute
initialization code
72

• Code Image Format

Header
Data structure
Runtime Module within the Image
Runtime Code
Initialization Code (Can be discarded after
execution)
Checksum
Unused space

• PCI Expansion ROM Header Format

Offset Length Value
Description 0h 1h 55h
ROM Signature,byte 1 1h 1h
AAh ROM Signature,byte 2 2h-17h 16h
XX Reserved(processor architecture
unique data) 18h-19h 2h XX
Pointer to PCI Data Structure
73

• Unique Data Area in ROM Header

Offset Length
Description 02h 1 Overall
size of the image 03h-05h 3
Entry point for the initialization code
( POST performs a far
call to initialize the device) 06h-17h
18 Reserved
74
PCI Data Structure
Format
Offset Length
Description 0 h 4
Signature, the string PCIR 4 h
2 Vendor
Identification 6 h 2
Device Identification 8 h
2 Pointer to Vital Product
Data Ah 2 PCI
Data Structure Length Ch 1
PCI Data Structure Revision Dh
3 Class Code 10h
2 Image Length
12h 2
Revision Level of Code/Data 14h 1
Code Type 15h 1
Indicator (Bit 7, 1 last
image) 16h 2
Reserved