CSL718 : Pipelined Processors

1
CSL718 Pipelined Processors

• Types of Pipelines
• Types of Hazards
• 16th Jan, 2006

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Types of Pipelined processors

• Degree of overlap
• Serial, Overlapped, Pipelined, Super-pipelined
• Depth
• Shallow, Deep
• Structure
• Linear, Non - linear
• Scheduling of operations
• Static, Dynamic

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Degree of overlap Depth
Serial
Shallow
Overlapped
Deep
Pipelined
4
Pipeline Structure
Linear Pipeline
A
B
C
Non-linear Pipeline
A
B
C
Sequence A, B, C, B, C, A, C, A
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Scheduling/timing alternatives

• Static
• same sequence of stages for all instructions
• all actions in order
• if one instruction stalls, all subsequent
  instructions are delayed
• Dynamic
• above conditions are relaxed
• higher throughput is achieved

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Dynamic Scheduling

• type 1 beginnings (decode) and endings (put
  away) in order
• type 2 only beginnings in order
• type 3 no order restrictions except
  dependencies
• type 1 extended beginnings in order, references
  that effect memory state are in order
• note that a memory reference may lead to page
  fault

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Pipelining and CPI
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Hazards in Pipelining

• Data dependencies gt Data hazards
• RAW (read after write)
• WAR (write after read)
• WAW (write after write)
• Resource conflicts gt Structural hazards
• use of same resource in different stages
• Procedural dependencies gt Control hazards
• conditional and unconditional branches,
  calls/returns

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Data Hazards
read/write
previous instr
read/write
current instr
delay 3
10
Structural Hazards
Caused by Resource Conflicts

• Use of a hardware resource in more than one cycle
  
• Different sequences of resource usage by
  different instructions
• Non-pipelined multi-cycle resources

11
Control Hazards
cond eval
target addr gen
branch instr
next inline instr
delay 2
target instr
delay 5

• the order of cond eval and target addr gen may
  be different
• cond eval may be done in previous instruction

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Handling Data Hazards
W
EX
previous instr
Data Forwarding
1
R
EX
current instr
W
previous instr
Instruction Reordering
2
R
current instr
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Analysis of Structural Hazards
Non-linear Pipeline
A
B
C
Reservation Table for X
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Analysis of Structural Hazards
Multi-functional Pipeline
A
B
C
Y
Y
Reservation Table for X
Y
for Y
Y
Y
Y
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Collisions with Initiation Interval 2
16
Collisions with Initiation Interval 5
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Latency Sequences and Cycles

• 1, 8, 1, 8, . (1, 8) avg 4.5
• 3, 3, 3, 3, . (3) avg 3
• 6, 6, 6, 6, . (6) avg 6
• Minimum Average Latency (MAL) ?

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Collision Free Scheduling for X
m . 2 1
1 0 1 1 0 1 0
Collision vector for X
1 collision 0 no collision
8
1 0 1 1 0 1 0
8
3
1
6
8
1 0 1 1 0 1 1
1 1 1 1 1 1 1
6
3
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Collision Free Scheduling for Y
m.2 1
1 0 1 0
Collision vector for Y
1 collision 0 no collision
5
1 0 1 0
5
1
3
5
1 0 1 1
1 1 1 1
3
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Latency Cycles from State Diagram

• Latency Cycles
• (1, 8) (1, 8, 6, 8) (3) (6) (3, 8) (3, 6, 3)
  
• Simple Latency Cycles (no figure repeats)
• (1, 8) (3) (6) (3, 8) (6, 8)
• Greedy Latency Cycles
• (1, 8) (3) - from different starting states

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Minimum Average Latency (MAL)

• MAL gt max no. of check marks in any row
• MAL lt avg latency of any greedy cycle
• avg latency of any greedy cycle lt
• no. of 1s in initial collision vector 1

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Upper Bound on MAL

• Consider a greedy cycle (k1,k2,..,kn)
• Let p no. of 1s in initial collision vector
• ? k1 lt p 1
• k2 lt 2 p - k1 2
• k3 lt 3 p - k1 - k2 3
• .
• kn lt n p - k1 - k2 - kn-1 n
• ? k1 k2 kn lt n p n ? MAL lt p 1