Sequential Logic

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Tutorial 2

• Sequential Logic

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Registers

• A register is basically a D Flip-Flop
• A D Flip Flop has 3 basic ports. D, Q, and Clock

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Registers

• Registers are edge sensitive to the clock
• On a rising edge of the clock, the output of the
  flip flop (Q) takes on the value of the input
  (D). This is known as clocking in.
• When its NOT the rising edge of the clock, Q
  doesnt change even if D does
• A register is often considered the most basic
  block of memory, because the value of D is stored
  in the register until the next clock cycle

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Sequential Circuits

• A sequential circuit is any digital design that
  has registers in it

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Processes

• In VHDL, sequential logic is described in a
  process
• process(clk)
• begin
• if rising_edge(clk)
• q lt d
• end if
• End process
• The rising_edge (or falling_edge) statement is a
  key word. Anything assignments in this if block
  is registered.

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Processes

• In a process, inside an if rising_edge block,
  all assignments are registered
• This means that on an assignment statement,
  everything to the LEFT of the lt is the output of
  a DFF and everything to the RIGHT is the input to
  a DFF

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Processes

• The previous example described a DFF. Lets
  describe something else.
• If rising_edge(clk) then
• a lt b
• c lt a
• end if
• What does the hardware look like?

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Processes
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Processes

• Lets mix it up a bit
• If rising_edge(clk) then
• a lt b
• c lt b
• end if
• What does the hardware look like?

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Processes
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Processes

• Lets put some combinational logic between those
  registers!
• If rising_edge(clk) then
• a lt b and c
• d lt a and b
• end if
• What does the logic look like?

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Processes
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Processes

• Registers can also feed back on themselves
• Process (clk)
• if rising_edge(clk) then
• a lt b or c
• d lt a xor d
• end if
• end process
• What does this hardware look like?

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Processes