CMOS Inverter: Digital Workhorse

1
CMOS Inverter Digital Workhorse

• Best Figures of Merit in CMOS Family
• Noise Immunity
• Performance
• Power/Buffer Ability
• Utilization of Design Scale
• Maxim
• When in doubt add an inverter!

2
CMOS Inverter
N Well
PMOS
2l
Contacts
Out
In
Metal 1
Polysilicon
NMOS
GND
3
CMOS Inverter Load Characteristics
4
CMOS Inverter VTC
5
Low Frequency Switching Threshold vs. Transistor
Ratio
6
Inverter Gain
7
Gain as a function of VDD
8
Simulated VTC
9
Impact of Process Variations I
2.5
Fast PMOS Slow NMOS
2
1.5
Typical
(V)
out
V
1
Fast NMOS Slow PMOS
0.5
0
0
0.5
1
1.5
2
2.5
V
(V)
in
10
Impact of Process Variations II

• Inverter Noise Margin
• Directly limited by Process Variations
• Also Function of Gain, Power Rail Noise, Temp

11
Propagation Delay
12
CMOS Inverter RC Transient Response Model
Low-to-high
High-to-low
V
V
DD
DD
R
p
V
V
out
out
C
C
L
L
R
n

• Assume Next Gate Switches at 50 swing
• Total Delay from sum of sequential gate delays

13
CMOS Inverter Propagation DelayRC Approximation
14
Transient Response (Equivalent R)
15
CMOS Inverter Propagation DelayHodges
Approximation
16
Transient Model (Equivalent I)

• Hodges Perscription for Iavg
• Average of Initial and Final Currents over swing
  of interest
• Easy since you know the voltages in CMOS Init0
  or Vdd Final Vdd/2
• Easy to add effects of other devices,
  capacitances and styles since current model

17
Device Sizing
(for fixed load)
Self-loading effect Intrinsic capacitances domina
te
18
Issues in Propagation Estimation

• Critical Path??
• Transitions are critical
• Asymmetric transistor sizing may be good!
• Dial in Noise/Level Shift/Favored Transition
• Load
• Interconnect
• Terminal
• Self-loading (non-linear)
• Output Swing
• Usually Vdd-gtVdd/2 or GND-gtVdd/2

19
NMOS/PMOS ratio
tpHL
tpLH
tp
b Wp/Wn
20
Propagation Details

• Most of Load is simple, but
• Non-linear Self Capacitance
• Drain Junction and Sidewalls
• Ratio Logic
• Other current sources/sinks
• Beware Body Effect
• Source at different potential from back

21
Impact of Rise Time on Delay
22
Inverter Sizing
23
Inverter Chain
In
Out
CL

• If CL is given
• How many stages are needed to minimize the
  delay?
• How to size the inverters?
• May need some additional constraints.

24
Inverter Delay

• Minimum length devices, L0.5mm
• Assume that for WP 2.5WN 2.5W
• same pull-up and pull-down currents
• approx. equal resistances RN RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network

2.5W
W
tpHL (ln 2) RNCL
tpLH (ln 2) RPCL
Delay (D)
Load for the next stage
25
Inverter with Load
Delay
RW
CL
RW
Load (CL)
tp k RWCL
k is a constant, equal to 0.69
Assumptions no load -gt zero delay
Wunit 1
26
Inverter with Load
CP 2.5Cunit
Delay
2.5W
W
Cint
CL
Load
CN Cunit
Delay kRW(Cint CL) kRWCint kRWCL kRW
Cint(1 CL /Cint) Delay (Internal) Delay
(Load)
27
Delay Formula
Cint gCgin with g ? 1 f CL/Cgin - effective
fanout R Runit/W Cint WCunit tp0
0.69RunitCunit
28
Apply to Inverter Chain
In
Out
CL
1
2
N
tp tp1 tp2 tpN
29
Optimal Sizing for Given N

• Delay equation has N - 1 unknowns, Cgin,2
  Cgin,N
• Minimize the delay, find N - 1 partial
  derivatives
• Result Cgin,j1/Cgin,j Cgin,j/Cgin,j-1
• Size of each stage is the geometric mean of two
  neighbors
• each stage has the same effective fanout
  (Cout/Cin)
• each stage has the same delay

30
Optimum Delay and Number of Stages
When each stage is sized by f and has same fanout
f
Effective fanout of each stage
Minimum path delay
31
Example
In
Out
CL 8 C1
1
f
f2
C1
CL/C1 has to be evenly distributed across N 3
stages
32
Optimum Number of Stages
For a given load, CL and given input capacitance
Cin Find optimal sizing f
For g 0, f e, N lnF
33
Optimum Effective Fanout f
Optimum f for given process defined by g
fopt 3.6 for g1
34
Impact of Self-Loading on tp
No Self-Loading, g0
With Self-Loading g1
35
Buffer Design
N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3
1
64
1
8
64
1
4
64
16
1
64
22.6
8
2.8
36
Power Dissipation
37
Where Does Power Go in CMOS?
38
Dynamic Power Dissipation
2
Energy/transition C
V
L
dd
2
Power Energy/transition
f
C
V

f
L
dd
Not a function of transistor sizes!
Need to reduce C
, V
, and
f
to reduce power.
L
dd
39
Transistor Sizing for Minimum Energy

• Goal Minimize Energy of whole circuit
• Design parameters f and VDD
• tp ? tpref of circuit with f1 and VDD Vref

40
Transistor Sizing (2)

• Performance Constraint (g1)
• Energy for single Transition

41
Transistor Sizing (3)
VDDf(f)
E/Ereff(f)
F1
2
5
10
20
42
Short Circuit Currents
43
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall gtgt
trise, but cant do this for cascade logic, so ...
44
Minimizing Short-Circuit Power
Vdd 3.3
Vdd 2.5
Vdd 1.5
45
Leakage
Sub-threshold current one of most compelling
issues in low-energy circuit design!
46
Reverse-Biased Diode Leakage
JS 10-100 pA/mm2 at 25 deg C for 0.25mm
CMOS JS doubles for every 9 deg C!
47
Subthreshold Leakage Component
48
Principles for Power Reduction

• Prime choice Reduce voltage!
• Recent years have seen an acceleration in supply
  voltage reduction
• Design at very low voltages still open question
  (0.6 0.9 V by 2010!)
• Reduce switching activity
• Reduce physical capacitance
• Device Sizing for F20
• fopt(energy)3.53, fopt(performance)4.47