MOSIS OVERVIEW OCTOBER, 2003

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MOSIS OVERVIEWOCTOBER, 2003

• César A. Piña
• http//www.mosis.org

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WHO WE ARE http//www.mosis.org

• Non-profit Microelectronics broker, dedicated to
  provide
• Low cost engineering samples of IC designs,
• Low-volume production service,
• 50 of MOSIS submicron runs are Dedicated
  runs (i.e., low volume production runs)
• Access to latest production proven technologies
• Single point of interface to its customers for
  additional services or products offered by
  partner vendors,
• Latest version of foundries design/electrical
  rules and spice models
• Educational Program for Microelectronics Design
• Experience - 22 Years of Operation
• Unique Only non-sponsored service in the world
  which provides access to multiple technologies
  fabricators

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TYPES OF CUSTOMERS

• Companies With Pilot Projects Requiring
  Engineering Samples for Proof of Concept
• Companies With Small Volume Production
  Requirements
• Government Agencies
• Universities Research, Education (VLSI Design
  Classes)

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WHAT WE DO

• Provide Access to multiple technologies and
  fabricators
• Organize Multiproject and Single Customer
  Dedicated Runs
• Collect and Merge Designs
• Provide Fully Checked Merged Designs to Mask Shop
• Production Compatible Masks to Foundry
• Mid Range Volumes (e.g. 500, 2000) Available
• Support Users
• Design Kit Distribution
• Handle Design Questions
• Design Rules, Modeling, IP, Etc.
• Include Reference Designs on MPW Runs (To verify
  yield)
• Work Closely With Design, IP Providers

http//www.mosis.org
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UFY2003 PERCENT SALES BY ACCOUNT TYPE
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Sample Multiproject Wafer http//www.mosis.org
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Sample Multiproject 0.18? Reticle
http//www.mosis.org
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Sample Multiproject 0.18µ Reticle
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THREE PHASES http//www.mosis.org

• Phase I 1981-1985 100 DARPA Direct Funding
• Phase II 1985-1994 - Multi-Agency Direct Funding
• DARPA 67 gt80
• Subsidized All Undersubscribed Runs
• NSA 26 gt 10
• NSF/DARPA Educational Program Starts 900k/yr.
• NSF 7 gt 5
• Commercial Customers 0 ? 5
• Helped to defray Government Costs by using excess
  area.
• Phase III 1994-2003 - Self-Sustaining Operations
• Commercial Customers are Only Source of Revenue
• Multi-Sponsor Ed. Program
• NSF (1994-1998)
• Commercial Firms
• MOSIS
• SRC/SIA (2000-2002)

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Available Technologies http//www.mosis.org

• TSMC CL035 0.35µ
• TSMC CL025/CM025 0.25µ
• TSMC CL018/CM018 0.18µ
• Peregrine SOI-SOS 0.50µ
• AMS BiCMOS (CMP) 0.8µ
• OMMIC GaAs (CMP) 0.2µ
• VITESSE InP HBT

• IBM 5HP/DM SiGe 0.50µ
• IBM 6HP/6DM SiGe 0.25µ
• IBM 6RF CMOS 0.25µ
• IBM 7SF CMOS 0.18?
• IBM 7WL CMOS 0.18? IBM 8SF
  CMOS 0.13?
• AMI ABN CMOS 1.50µ
• AMI C5N CMOS 0.50µ
• AMI C3N CMOS 0.35µ

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SIA 2001 RoadmapMOSIS Roadmap
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Gate Delay (Ps) vs. Feature Size 31 Stage CMOS
Ring Oscillator
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PHOTOLITHOGRAPHY
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FAB COSTS

• Lithography has become the most significant cost
  item in deep submicron fab
• Wafer and mask costs relatively the same until
  the 0.35µ node
• Different lithography technologies
• 1X Stepper Lithography
• Medium payload 900 sqmm 1.5µ is lowest
  practical limit
• 5X Stepper Lithography
• Small Payload 480 sqmm max.
• Technology of choice for 1.2µ and below
• 0.5µ - 1.6µ mask tech. Straightforward
• 0.18µ - Mix and Match 5X and 4X Stepper/Scanner
  Reticles
• VERY EXPENSIVE 25x cost of 1.5 µ masks
• 0.13 µ-Mix and Match 5 and 4x
• US 500k-750k per mask set

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Optical Lithography Resolution Limits
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RESOLUTION ENHANCEMENTSOPTICAL PROXIMITY
CORRECTIONS
Hammerhead
Jogs
Inside serifs (clear)
Outside serifs (chrome)
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RESOLUTION ENHANCEMENTSOPC For Contacts

• Optical Proximity Correction
• No OPC OPC Applied
• Diffraction at corners of small vias and/or
  contacts results in incomplete resist exposure.
• Not needed for 0.35um or larger
• Is required for S lt 0.2 um

CONTACT ON WAFER 0.5 X 0.5um CONTACT ON MASK
2.5 X 2.5um
CORNER BOX DIMENSIONS 0.5um x 0.5um
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RESOLUTION ENHANCEMENTSPHASE SHIFT MASKS

• PHASE SHIFT MASKS
• Masks very expensive
• Geometry dependent- Difficult to get arbitrary
  shapes

Incoming radiation Chrome Pattern Groove Depth
1/2 wavelength of light Interference effects
between light passing through the groove and the
middle of the feature, produce a sharp line.

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DEEP SUBMICRONPLANARIZATION
Passivation Layer
Metal Lines
If metal lines are close together, passivation
layer can be planarized
to the required degree, otherwise, additional
metal lines have to be added to the designs
photo masks. This process should be transparent
to the designer.
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SUBMITTED GEOMETRY
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METAL FILL ADDITION TOSUBMITTED GEOMETRY
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NUMBER of MASKSvsFEATURE SIZE
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TYPICAL FILE SIZE (Mb)vsFEATURE SIZE (?)
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WAFER AND MASK COSTS NORMALIZED TO COSTS OF 1.5?
FEATURE SIZE
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MOSIS EDUCATIONAL PROGRAM (MEP)
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EDUCATIONAL PROGRAM

• Description
• The MEP provides free fabrication of integrated
  circuits designed by students at accredited
  educational institutions in the U.S., Central and
  South America, Spain, New Zealand and Australia
• Geographical limits set by available MOSIS
  resources
• Two types of accounts
• INSTRUCTIONAL
• RESEARCH
• Eligibility
• Fabrication of student designs is available to
  accredited universities who agree to the
  following terms
• Design, simulation, and testing tools must be
  specified
• A report must be sent to MOSIS for each
  fabricated circuit.
• Further Details can be found at
  http//www.mosis.org

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ACCOUNT DESCRIPTIONS

• INSTRUCTIONAL Program
• Designs from students in organized classes
  Undergraduate and Graduate
• Enrollment at beginning of the Quarter/Semester
• Each student is allocated a Tiny Chip Unit of
  area
• Detailed reports on chip test results are
  required for every chip fabricated
• The chip worked as expected is not a sufficient
  report
• Technologies
• CMOS Analog/digital 1.5µ, 0.5µ
• 1.5µ Technology Tiny Chip Unit size is 2.2mm X
  2.2mm
• 0.5µ Technology Tiny Chip Unit size is 1.5mm X
  1.5mm

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ACCOUNT DESCRIPTIONS

• RESEARCH Program
• Restricted to non-sponsored research Thesis or
  research projects
• Mini-proposal (2-3 pg., or more if necessary)
  required Design description, design tools,
  testing, simulation, purpose.
• One design per proposal Must be clear and
  detailed, including desired technology and an
  accurate chip size estimate.
• Final report required upon completion
• May be a copy of an internal report or a
  published paper
• Projects are selected by MOSIS based on merit and
  originality
• Selected designs are fabricated in regularly
  scheduled MOSIS runs,
• on a space available basis.
• Technologies
• CMOS 1.5µ, 0.5µ, 0.35µ, 0.25µ, 0.18µ, 0.13µ
  SiGe 0.5µ 0.25µ

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Program Oversight and Institution Eligibility

• Program Oversight
• MOSIS Advisory Council for Education
• University Professors, SRC, Industrial
  Contributors
• Institution Eligibility
• All U.S. Universities
• Non-U.S. Universities
• Funding Provided Solely by MOSIS
• 1999 Instructional and Research MEP extended to
  include Latin American, New Zealand and
  Australian Universities
• 2002 Research MEP Access extended to include
  Europe
• Current geographical restrictions are set by
  available MOSIS resources.

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Educational ProgramFunding

• 1984-1994 Funding was provided solely by
• National Science Foundation (NSF) (575k/yr)
• Defense Advanced Projects Agency (DARPA)
  (375k/yr)
• 1995-1999 Funding provided by
• National Science Foundation (NSF)
• AMI, HP Wafer run donations
• MOSIS Administrative costs
• 2000-2003
• AMI Wafer run donations 1.5um 0.5um
  (4-5runs/yr)
• IBM Wafer fab 0.5um 0.25um SiGe
• SIA/SRC Instructional Advanced Program Fab
  (335k/yr)
• Dupont Discounted photomasks for educational
  only runs.
• MOSIS Provides
• All administrative expenses (110k/yr)
• Instructional and advanced Program Fab
  (600k/yr)

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SUMMARY

• Low Cost Prototyping
• Regularly Scheduled Prototype Runs
• Low Volume Production
• Access to Latest TSMC and IBM Production
  Technology
• Access to Important Third Party Resources
• Monitors Quality of Vendors and Processes
• Privately Funded VLSI Educational Program

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PROJECT SUBMISSION
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MEP PERFORMANCEand Technologies

• Ten Years 1990 through 1999 inclusive
• 12,130 Student Designs Processed
• gt 50,000 Students Participated
• Total of 195 U.S. Universities
• 1984-2003 Technologies Offered
• 1984-1987 NMOS (3-4?), CMOS (2-3?)
• 1988-1997 CMOS (2?)
• 1997-1999 CMOS (2, 1.5, 0.5, 0.35, 0.25?)
• 1999- 2000 CMOS(1.5, 0.5, 0.35, 0.25?) SiGe
• 2001- gt CMOS(1.5, 0.5, 0.35, 0.25, 0.18?)
  SiGeSOS

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MOSIS Web Forms http//www.mosis.org

• Project submission, tracking, etc.
• Secure or non-secure

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COMPATIBLE DESIGN LIBRARIES

• Artisan
• Commercial Firms
• Free Digital Libraries, I/Os Memories
• TSMC 0.25µ and 0.18µ processes
• Work with Commercial EDA tools Avant!, Cadence,
  Synopsis
• Universities
• Complete front end views of core I/O cells
• Behavioral, synthesis, simulation, PR
• No GDS, MOSIS Instantiates the cells

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COMPATIBLE DESIGN LIBRARIES

• Barcelona Design
• Tools services for analog synthesis of A/Ds,
  D/As, Op-Amps, PLLs
• AMI 0.5µ, TSMC 0.35µ, 0.25µ, 0.18µ Processes
• LEDA Systems
• Analog RF Cells for the TSMC 0.25µ, 0.18µ
  Processes
• Nurlogic
• Digital, Analog/RF Special I/O Cells for
• TSMC 0.25µ, 0.18µ Processes
• IBM 6HP SiGe 0.25µ

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Standard Data Preparation http//www.mosis.org

• Project Check
• Checks design syntax
• Checks layer names
• Computes the size, counts the pads
• Checks actual values with declared values
• DRC available (optional)
• Data Prep
• Sizing, logical operations (inc. OPC)
• Add CMP fill

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GENERAL QUESTIONS

• IMPORTANT Get the GDS file into the system
  properly, not as an attachment to an e-mail
  (please NEVER do this)
• MOSIS does not require require a seal on the edge
  of your design
• MOSIS will install a seal ring which is part of
  the definition of the scribelines for the
  reticle.
• This ring will not necessarily be in close
  proximity to your layout,
• If you want a "guardring for whatever reasons
  (of your own), then you should draw it yourself

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DESIGN RULE CHECKING

• The design rules which must be followed are
  posted in the form of DRC decks and Design Rule
  documents (MOSIS secure doc. server)
• MOSIS cannot possibly tell you that violating
  those rules is safe.
• MOSIS routinely uses DRACULA for TSMC 0.25,
• BUT moving to Mentor Graphics' "Calibre" for
  more advanced technologies.
• DRACULA works well enough for DRC and antenna
  checking.
• For checking connectivity, MOSIS prefers the
  Calibre LVS deck,
• Since the DRACULA decks do not handle MiM metals
  correctly, this is critical when checking for
  shorts.
• Be sure and select the proper variants of the
  DRC decks
• for example, if you are using thick-top-metal,
  there is a special set of
• thick-top-metal decks
• if you are using mixed-mode features such as MiM,
  or strange threshold devices etc., use the
  mixed-mode decks etc.
• Important, no two tools ever give the same flags
  for the same layout.

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? BASED (Scalable) DESIGN RULES

• RULES
• Mead-Conway, 1979
• NMOS
• CMOS Rules
• JPL 1983
• SCMOS
• 3?-1.2 ?
• SCMOS_SUBM
• Sub-micron processes
• SCMOS_DEEP
• Modified SCMOS_SUBM
• For 0.25 ? and below

• ADVANTAGES
• Simplicity
• Easy to transfer designs to another process
• Process Independent for all MOSIS processes
• Suitable Designs
• R-F/ Analog designs may need precise vendor rules
• Most other designs can use these rules.
• For 0.25? the area penalty is 3-5 compared to
  vendor rules. Speed penalty is negligible!

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ADVANTAGES OF ? BASED SCALABLE RULES

• Simplicity
• Almost Completely Process Independent for all
  MOSIS processes
• Suitable Designs
• R-F Analog designs may need precise vendor rules
• Most other designs can use these rules with minor
  performance or area deficits
• For 0.25? the area penalty is 3-5 compared to
  vendor rules. Speed penalty is negligible
• Easy to transfer designs to another process
• One MOSIS customer has used the SCMOS simplest
  rules in scaling a core design from 1.6? to 0.18?
  !

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UFY02 - Educational Projects by Technology
Technology MOSIS Funded SRC Funded Ed. Runs SRCAMI TOTAL
0.18 9 3 0 12
0.25 1 7 0 8
0.35 6 8 0 14
0.50 99 106 240 445
1.5 27 141 41 209
SiGe 0.50 6 0 0 6
TOTALS 148 265 281 694
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Optical Lithography Resolution Limits
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PHASE SHIFT MASK S vs. BINARY MASK S

• BINARY MASKS
• Clear and chrome only
• Transmits light
• Blocks/Reflects light
• Limited by
• k1 and N.A. of Stepper
• ? of light
• OPC extends useful range
• 0.35µ and 0.25 µ features
• Fastest mask cycletime
• (Lowest cost)

• PHASE SHIFT MASKS
• 0/60/120/180º Chrome
• Transmits with phase, reduces cross-talk
• Chrome blocks light
• Phase edge is dark
• Multiphase nulls defects transitions
• Enhances latitude, DOF, and/or resolution
• Can be combined with OPC
• Most involved flow and longest cycle time
• VERY EXPENSIVE

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Relative Speed vs. Feature Size