MMU

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MMU Memory Management Unit Chapter 14
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Presented by

• Group13
• Asmaa Rabie Abdualaziz
• Islam Ameen Abdualaziz
• Doaa Ahmed Mohamed
• Sherif Mohamed Medhat

• Presented to
• Dr.Amr Wassal
• CMP 2012

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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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What will we learn from chapter?

• Learn basics of ARM MMU and some basic concepts
  that underlie the use of the virtual memory

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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Introduction

• Virtual addresses Assign by Compiler and Linker

• Physical addresses Access the actual hardware
  components

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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Moving From An MPU To An MMU

• What is the difference between active and dormant
  region?
• Difference Between MPU MMU

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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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How Virtual Memory works
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0x0800
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The components of a virtual memory system
Virtual memory
Physical memory
MMU
Page tables
PTE
Page frame
Relocation register
Page
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Defining Regions Using Pages
Virtual Memory
Physical Memory
Page tables
Stack
Region 3
RAM
Data
Region 2
Flash
Text
Region 1
Page frame
PTE
Page
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Multitasking and The MMU
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Memory Organization in a Virtual Memory System
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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Details Of The ARM MMU

• Page tables
• Translation Lookaside Table (TLB)
• Domain and access permission
• Caches and write buffer
• CP15 c1 control register
• Fast Context Switch Extension

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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Page Table

• L1
• Entries for translating 1 MB pages
• Pointers to the starting address to level 2 page
  tables
• L2
• Fine page table
• Coarse page table

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Level 1

• Level 1 page table accepts four types of entry
• A 1MB section translation entry
• A directory entry that points to a fine L2 page
  table
• A directory entry that points to a coarse L2
  page table
• A fault entry that generates an abort exception
  

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L1 page entries
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L1 page entries
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L1 page entries
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L1 page entries
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Translation Table Base Address
The CP15c2 register holds the translation table
base address (TTB)an address pointing to the
location of the master L1 table in virtual
memory.
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Level 2

• Level 2 page table accepts four types of entry
• A large page entry defines the attributes for a
  64 KB page frame.
• A small page entry defines a 4 KB page frame.
• A tiny page entry defines a 1 KB page frame.
• A fault page entry generates a page fault abort
  exception when accessed.

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L2 page entries
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L2 page entries
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L2 page entries
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L2 page entries
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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Translation Lookaside Buffer

• Fully associative cache of recently used
  translations
• Stores Access permission set
• Use round-robin replacement algorithm
• Supports flush and lock operations

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L1 Page table virtual-to-physical memory
translation using 1 MB sections
offset
Base
Virtual address
L1 master page table
Page table entry
Translation table base address
Selects physical memory
offset
physical address
Base
Copied to TLB
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Two-level virtual-to-physical address
translation using coarse page tables
Virtual address
Page offset
L2 offset
L1 offset
Step 1
L1 master page table
Coarse L2 page table
L2 Page table entry
Step 2
L1 Page table entry
Translation table base address
L2 Page table base address
Physical Base
Page offset
physical address
Copied to TLB
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TLB Operations
Lock down
42f4
6726
6726
3889
ab56
35de
Flush
9001
9001
f8d9
8845
8787
7842
8fd3
8fd3
9999
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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Domain Access permission

• There are two different controls to manage a
  tasks access permission to memory.
• Primary is the Domain.
• Secondary is access permission set in the page
  tables.
• Domain control basic access to virtual memory by
  isolating on area of memory from another when
  sharing common virtual memory map

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Domain bit access bit assignment
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Page Table-Based Access permission
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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Caches and Write Buffer
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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Coprocessor 15 and MMU configuration
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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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Fast Context Switch Extension (FCSE)

• Enables multiple independent tasks to run in a
  fixed overlapping area of memory
• FCSE eliminates the need of flushing the cache
  and TLB
• Uses process ID to convert overlapping virtual
  address(VA) to a unique modified virtual
  address(MVA)
• MVA VA (0x200000 process ID)

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Steps to perform context switch when using FCSE

1. Save active tasks context and put the task in
   dormant state
2. Write the awakening tasks process ID to CP15c13
3. Locate set the current tasks' domain to no access
   and the awakening tasks domain to client access
   by writing to cp15c3c0
4. Restore the context of awakening task
5. Resume execution of re stored task

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Agenda

• 1. What we will learn from chapter ?
• 2. Introduction
• 3. Moving From An MPU To An MMU
• 4. How Virtual Memory works
• 4.1 The components of a virtual memory system
• 4.2 Defining Regions Using Pages
• 4.3 Multitasking and The MMU
• 4.4Memory Organization in a Virtual Memory System
  
• 5. Details Of The ARM MMU
• 6. Page Table
• 6.1 Level 1
• 6.2 Translation Table Base Address
• 6.3 Level 2
• 7. Translation Lookaside Buffer
• 7.1 L1 Page table virtual-to-physical memory
  translation using 1 MB sections
• 7.2 Two-level virtual-to-physical address
  translation using coarse page tables
• 7.3 TLB Operations
• 8. Domain Access permission
• 9. Caches and Write Buffer

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A small virtual memory system

• 3 Tasks
• The same execution region
• 256 MB of memory for peripheral devices
• Very simple example!

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How to setup the MMU?

1. Define a fixed system software region
2. Define 3 virtual memory maps for the 3 tasks
3. Locate regions in step 1 2 into the physical
   memory
4. Define and locate the page tables within the page
   table region
5. Data structures for regions and page tables
6. Initialize the MMU, caches, and write buffer
7. Set up a context switch routine to switch between
   tasks

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1- Fixed system software region

• The OS kernel code and data
• Fixed addressing to avoid the complexity of
  remapping when changing to a system mode context.

• Shared libraries
• The transition routines for switching from
  privileged mode to user mode during a context
  switch

• 16 KB for the master table
• 1 KB each for the four
• L2 tables.
• 12 KB free memory

• Controls the system device I/O space
• Noncached Nonbuffered region

1MB
32 KB
32 KB
32 KB
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2- Define Virtual Memory Maps for Each Task

• Text, data, and stack of the running user task.
• Remap the Task region on task switch

• Discussed!

32 KB
32 KB
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3- Locate Regions in Physical Memory
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4- Define and Locate the Page Tables
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5- Define Page Table and Region Data Structures

• Page Table struct
• typedef struct
• unsigned int vAddress //Address of a 1
  MBsection of virtual memory
• unsigned int ptAddress //Location in
  virtual memory.
• unsigned int masterPtAddress //Address of the
  parent master L1 page table.
• unsigned int type //COARSE, FINE,
  or MASTER
• unsigned int dom // Domain value
• Pagetable

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5- Define Page Table and Region Data Structures

• Page Table struct
• typedef struct
• unsigned int vAddress //Address of a 1
  MBsection of virtual memory
• unsigned int ptAddress //Location in
  virtual memory.
• unsigned int masterPtAddress //Address of the
  parent master L1 page table.
• unsigned int type //COARSE, FINE,
  or MASTER
• unsigned int dom // Domain value
• Pagetable

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5- Define Page Table and Region Data Structures

• Example
• / vAddress, ptAddress,
  masterPtAddress, type , dom/
• Pagetable systemPT 0x00000000, 0x1c000,
  0x18000, COARSE, 3

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5- Define Page Table and Region Data Structures

• Region struct
• typedef struct
• unsigned int vAddress // Address of the region
  in virtual memory
• unsigned int pageSize //Size of a virtual page
• unsigned int numPages // Number of pages in the
  region
• unsigned int AP // Region access permissions
• unsigned int CB // Cache and write buffer
  attribute
• unsigned int pAddress // Address of the region
  in virtual memory
• Pagetable PT // pointer to the Pagetable in
  which the region resides
• Region

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5- Define Page Table and Region Data Structures

• Example
• / vAddress, pageSize, numPages, AP,
  CB , pAddress , PT /
• Region kernelRegion 0x00000000, 4, 16, RWNA,
  WT, 0x00000000, systemPT

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6- Initialize the MMU, caches, and write buffer

1. Initialize the page tables in main memory by
   filling them with FAULT entries
2. Fill in the page tables with translations that
   map regions to physical memory.
3. Activate the page tables.
4. Assign domain access rights.
5. Enable the MMU and cache hardware

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6- Initialize the MMU, caches, and write buffer

• 1)Initialize the page tables
• mmuInitPT(Pagetable )
• Fill the Page Table by Fault entries
• The size of the table is determined by reading
  the type of Page table defined in pt-gttype
  (Master, Coarse, Fine)

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6- Initialize the MMU, caches, and write buffer

• 2)Filling Page Tables with Translations
• mmuMapRegion(Region region )
• switch (region-gtPT-gttype)
• case SECTION
• mmuMapSectionTableRegion(region)
• case COARSE mmuMapCoarseTableRegion(re
  gion)
• case FINE
• mmuMapFineTableRegion(region)

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6- Initialize the MMU, caches, and write buffer

• 3) Activating a Page Table
• Why?
• mmuAttachPT(Pagetable pt)
• It activates an L1 master page table by placing
  its address into the TTB in the CP15c2c0
  register
• Or activates an L2 page table by placing its base
  address into an L1 master page table entry

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6- Initialize the MMU, caches, and write buffer

• 4) Assigning Domain Access and Enabling the MMU
• All active memory areas must have a domain
  assignment
• The minimum domain configuration places all
  regions in the same domain and sets the domain
  access to client access.
• void domainAccessSet(unsigned int value, unsigned
  int mask)

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6- Initialize the MMU, caches, and write buffer

• 5) Enable the MMU
• / Call the previous functions /
• void mmuInit()
• mmuInitPT(Pagetable ) //Init the Page
  Tables
• mmuMapRegion(Region region ) //Map The
  regions
• mmuAttachPT(Pagetable pt) //Activate the Page
  Table
• void domainAccessSet(unsigned int value,
  unsigned int mask) //Set Domain Access

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7- Establish a Context Switch Procedure

1. Save the active task context and place the task
   in a dormant state.
2. Flush the caches
3. Flush the TLB to remove translations for the
   retiring task
4. Configure the MMU to use new page tables
5. Restore the context of the awakening task
6. Resume execution of the restored task

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Any Questions