RapUp

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RapUp

• Dynamic Allocation of Memory in C
• Last HW Exercise
• Review for Final
• Final Exam Next Thursday Same Time / Same Place

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Dynamic Storage Allocation from the Heap
In Java, memory is allocated only to Objects, and
freeing of memory is done automatically by the
garbage collector when an Object is no longer
accessible. This was to eliminates memory leaks
in Java, BUT if links to stale Objects remain,
the garbage collector can never act on them.
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Last Homework (HW12)

• C Program Organization
• Pre Main Code Establish Stack, Init R4 R5
• Main Function
• Scanf Function - Replace this Physical
  Space with
• 
  Your Scanf Function (which accepts a pointer)
• 
  Your Interrupt Service Routine
• Printf Function
• Global Data Area ? R4
• . . . . . . . . . . . .
• Stack ? R6 (and ? R5)
• Note Remember that your Scanf Function must

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LC-3 ArchitectureData paths Control Signals
PSW (Program Status Word) Bits 15
10 9 8 2 1 0
S Priority
N Z P
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LC-3 Instructions

• Addressing Modes
• Register
• (Operand is in one of the 8 registers)
• PC-relative
• (Operand is offset from where the PC points
• - offsets are sign extended to 16 bits)
• Base Offset (Base relative)
• (Operand is offset from the contents of a
  register)
• Immediate
• (Operand is in the instruction)
• Indirect
• (The Operand points to the real address of
  Operand
• rather than being the operand)
• Note The LC-3 has No Direct Addressing Mode

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LC-3 Simulator Screen
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Traps

• Execute TRAP vector number - Service
  Routine Address
• Trap Vectors are at memory locations
  000000FF
• Trap Vectors contain addresses of Pre
  written (?) Service Routines
• 2) PC is stored in R7 (save the return
  address)
• 3) Address of Trap Service Routine loaded into
  PC (addr of service routine)
• 4) Service Routine Program executed
• Trap service routine program ends with an RET (to
  return to calling prog)
• R7 loaded into PC

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Subroutines

• 1) Execute JSR offset or JSRR rn - Call
  Subroutine or Method
• Location of Subroutine is specified in the
  Instruction
• 2) PC stored in R7 (store return address)
• 3) Address from JSR offset or JSRR rn is loaded
  into PC (beginning of subr)
• 4) Subroutine is executed
• R0 likely contains passed parameter (or address)
• R5 may be used to return error message
• R0 likely contains return parameter (or address)
• 5) Subroutine program ends with an RET ( R7
  loaded into PC)
• Can you pass (return) two parameters ?
• Can a subroutine call another subroutine ?
• How does this mechanism support recursion?

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Stack R6 is the Stack Ptr Push Push ADD
R6, R6, -1 Decrement Stack Ptr
STR R0, R6, 0 Push R0 onto
Stack Pop Pop LDR R0, R6, 0 Pop
Data off of Stack (into R0) ADD R6, R6, 1
Increment Stack Ptr What do we need to do
to facilitate nested subroutines ? Push R7
(containing the return PC) onto the Stack
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Allocating Space for Variables
x0000
Trap Vectors

• Global data section
• All global variables stored here(actually all
  static variables)
• R4 points to Global Variables
• Run-time stack
• Used for local variables
• (among other things)
• R6 points to top of stack
• R5 points to top frame on stack
• New frame created for each blockor scope (goes
  away when block exited)
• Accessing a variable
• Global LDR R1, R4, x
• Local LDR R2, R5, -y
• Offset distance from beginning of storage area

x0100
Intr Vectors
x0200
Op Sys
x3000
instructions
PC
R4
global data
Heap
R6
run-time stack
R5

xFE00
Device Registers
xFFFF
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Context Frame (Activation Record) Format(Note
you will see that there is some inconsistency as
to where the Frame begins)
Function stacked stuff ..
.. Local Variables Callers Frame Pointer
(R5) Callers R7 (contains callers PC) Function
Return Value Function Pass Value 1
.. Function Pass Value n
R6

R5
- - - - - - - -
Caller pushes arguments (last to first). Caller
invokes subroutine (JSR). Callee allocates
return value, pushes R7 and R5. Callee allocates
space for local variables. Callee executes
function code. Callee stores result into return
value slot. Callee pops local variables, pops R5,
pops R7. Callee returns RET (or JMP R7). Caller
loads return value and pops arguments. Caller
resumes computation


Frame
.. Local Variables
Previous R5
- - - - - - - -
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Stack Snapshot

• Stk in Func4
• xEFE2
• xEFE3
• xEFE4
• xEFE5 (Func4 local var) lt-
  FramePtr (Func4)
• xEFE6 R5 FramePtr (xEFEA)
• xEFE7 R7 Saved PC (x3071)
• xEFE8 return value from Func4
• xEFE9 pass value to Func4 (C 8)
• xEFEA (Func3 local var) lt- FramePtr (Func3)
• xEFEB R5 FramePtr (xEFEF)
• xEFEC R7 Saved PC (x3059)
• xEFED return value from Func3 space
• xEFEE pass value to Func3 (C 8)
• xEFEF (Func2 local var) lt- FramePtr (Func2)
• xEFF0 R5 FramePtr (xEFF4)
• xEFF1 R7 Saved PC (x3041)
• xEFF2 return value from Func2 space
• xEFF3 pass value to Func2 (C 8)

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Program Context Implications

• What are the Program Context implications of
• Executing a Trap Routine ?
• The PC must be saved and restored (Done by TRAP
  RET)
• (Registers must be restored by Trap Routine -
  
• It is assumed all other state values
  effectively remain unchanged)
• Executing a Subroutine (or Function, or Method) ?
• The PC must be saved and restored (Done by JSR or
  JSRR, RET)
• (Registers must be restored by Trap Routine -
• It is assumed all other state values
  effectively remain unchanged)
• Executing an Interrupt ?
• The PC, SP, PSW must be saved and restored
  (Done by Supervisor RTI)
• (Registers must be restored by Interrupt
  Service Routine -
• It is assumed all other state values
  effectively remain unchanged)

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Program Context Includes PC, PSW (PSR),
SP (R6) Program Status Word (in the Program
Status Register) PSW (PSR) PSR15
Privilege Bit - 0 for Privileged (Supervisor)
State 1 for User State
PSR108 Priority Bits - Eight Levels (7
is the highest) PSR20 Condition
codes - N, Z, P
Stack Pointer ( R6 USP or R6 SSP )
USP SSP User Stack Pointer Supervisor
Stack Pointer USP.saved
SSP.saved Two auxiliary registers that are used
to store the value of the
Stack Pointer (User or Supervisor) that is not
in use. This is done
automatically when the PSR15 bit is switched.
- When in User Mode (PSR15
1), R6 is the User Stack Pointer
and SSP.Saved contains the Supervisor Stack
Pointer. - When in Supervisor
Mode (PSR15 0), R6 is the Supervisor Stack
Pointer and USP.Saved contains
the User Stack Pointer.
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Interrupt Components
Device (Keyboard shown here as example)
Memory
Keyboard Status Register Keyboard Data
Register Keyboard Priority 0 to
7 Device Interrupt Vector 180 to 1FF
(Note device actually sends 00-FF to CPU)
CPU PC (Program Counter) R6 (Stack
Pointer) PSR (Program Status Word) Bits
15 10 9 8 2
1 0 S Priority
N Z P USP.saved (User Stack
Pointer Storage) SSP.saved (Supervisor Stack
Pointer Storage)
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Interrupt Example

Intr Vectors
Supervisor Stack
Program flow
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Interrupt Process This is important to
understand !
An interrupt can occur anywhere in a computer
program, unlike Trap Calls or
Subroutine Calls which occur exactly where you
place them !

• 1) Programmer Action
• Loads a Service Routine for the Device, and
  enters its Entry Addr in the Interrupt Vector
  Table
• Enables Interrupts by setting intr enable
  bit in Device Status Reg
• 2) Device Action to Request an Interrupt
• When device needs service, (done or ready
  bit set, and interrupt enable bit set) and
• - its priority is higher than the
  priority of the Presently Running Program, and
• - execution of the present
  instruction is complete, then
• The Device submits an Interrupt
  Request, and when granted, supplies CPU with
  Interrupt Vector
• 3) CPU Action to Initiate Service of the
  Interrupt
• When the CPU accepts the Interrupt Request
  (Priority higher than the present program
  Priority)
• - The CPU goes into Privileged Mode
  (PSR bit 15 cleared)
• - R6 ? USP.saved register and
  SSP.saved ? R6, the stack pointer
• - The Processor saves the state
  (context) of the program (must be able to return)
• The PC and the PSR are
  PUSHED onto the Supervisor Stack (Other regs are
  not. Why?)
• - Priority level is set (established
  by the interrupting device) and the CCs are
  cleared
• Then, the PC is loaded with the service
  routine address (between 180 and 1FF).
• (Based upon the Device
  supplied Interrupt Vector 00 to 7F)

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Example Parameter Passing by Reference

• include ltstdio.hgt
• void NewSwap(int firstVal, int secondVal)
• int main()
• int valueA 3
• int valueB 4
• NewSwap(valueA, valueB)
• return valueA / returns 4 /
• void NewSwap(int firstVal, int secondVal)
• int tempVal / Holds firstVal when swapping /

Initially After
firstValSecondVal At the end
?
Snapshots During the Exchange
What happened differently using pass by
reference, rather than pass by value ?
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(No Transcript)