Csci 136 Computer Architecture II

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Csci 136 Computer Architecture II Data Hazard,
Forwarding, Stall

• Xiuzhen Cheng
• cheng_at_gwu.edu

2
Announcement

• Homework assignment 10, Due time Before class,
  April 12
• Readings Sections 6.4 6.5
• Problems 6.17-6.19, 6.21-6.22, 6.33-6.36,
  6.39-6.40 (six of them will be graded. Your TA
  will give hints in the lab sections.)
• Project 3 is due on April 17, 2005
• Final Thursday, May 12, 1240AM-240PM
• Note you must pass final to pass this course!

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The Big Picture Where are We Now?

• The Five Classic Components of a Computer
• Current Topics
• Datapath Control
• Data Hazard
• Hazard Detection, Data Forwarding, Stall

Processor
Input
Control
Memory
Datapath
Output
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Recap The Complete Pipelined Datapath
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Data Hazards

• The input of some instruction depends on the
  output of another instruction which is still in
  the pipeline
• An example what if initially 2-20, 110, 32?

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Resolving Data Hazard

• Write reg in the first half of CC and read it in
  the second half of that CC.
• Insert NOP instructions, or independent
  instructions by compiler
• Detect the hazard, then forward the proper value
• The good way

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Data Hazard Detection

• From the example, 1. sub 2, 1, 3 2. and
  12, 2, 5 3. or 13, 6, 2
• And and or needs the value of 2 at ALU stage
• For first two instructions, hazard happens when
  sub is in MEM stage, while and is in ALU stage
• For the first and third instructions, hazard
  happens when sub is in WB stage while or is in
  ALU stage
• Hazard detection conditions EX hazard and MEM
  hazard
• 1a. EX/MEM.RegisterRd ID/EX.RegisterRs
• 1b. EX/MEM.RegisterRd ID/EX.RegisterRt
• 2a. MEM/WB.RegisterRd ID/EX.RegisterRs
• 2b. MEM/WB.RegisterRd ID/EX.RegisterRt

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In-class Exercise

• Classify the dependencies in the following
  sequence sub 2, 1, 3 and 12, 2,
  5 or 13, 6, 2 add 14, 2, 2 sw 15,
  100(2)

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Add Forwarding Paths
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Refine the Hazard Detection Condition

• Conditions 1 and 2 are true, but the instruction
  in MEM stage and WB stage do not write
• No hazard
• Check RegWrite signal in the WB field of the
  EX/MEM and MEM/WB pipeline register
• Condition 1 and 2 are true, but RegisterRd is 0.
• No hazard
• For code sequence add 1, S1, S2, add 1, 1,
  3, add 1, 1, 4
• The third instruction depends on the second, not
  the first
• Should forward the ALU result from the second
  instruction
• For MEM hazard, EX/MEM.RegisterRd ! ID/EX.Regist
  erRs EX/MEM.RegisterRd ! ID/EX.RegisterRt

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New Hazard Detection Conditions

• EX hazard if ( EX/MEM.RegWrite and
  (EX/MEM.RegisterRd ! 0) and
  (EX/MEM.RegisterRd ID/EX.RegisterRs)) ForwardA
  10
• if ( EX/MEM.RegWrite and
  (EX/MEM.RegisterRd ! 0) and
  (EX/MEM.RegisterRd ID/EX.RegisterRt)) ForwardB
  10

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New Hazard Detection Conditions

• MEM Hazard if ( MEM/WB.RegWrite
  and (MEM/wB.RegisterRd !0) and
  (EX/MEM.RegisterRd ! ID/EX.RegisterRs) and
  (MEM/wB.RegisterRd ID/EX.RegisterRs)) ForwardA
  01
• if ( MEM/WB.RegWrite and
  (MEM/wB.RegisterRd !0) and
  (EX/MEM.RegisterRd ! ID/EX.RegisterRt) and
  (MEM/wB.RegisterRd ID/EX.RegisterRt)) ForwardB
  01

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Complete Datapath with Forwarding Path
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Example

• Show how forwarding works with the following
  instruction sequence sub 2, 1, 3 and 4,
  2, 5 or 4, 4, 2 add 9, 4, 2

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Clock 3
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Clock 4
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Clock 5
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Clock 6
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Adding ALUSrc Mux to the Datapath
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Forwarding Cant do Anything!

• When an instruction reading a register following
  by a load instruction that writes the same
  register, forwarding does not solve the data
  hazard
• Stall the pipeline

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Stalling the pipeline Bubble
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Hazard Detection

• At ID stage, why?
• Detection logic if ( ID/EX.MemRead
  and ( (ID/EX.RegisterRt IF/ID.RegisterRs)
  or (ID/EX.RegisterRt IF/ID.RegisterRt)
  )) stall the pipeline
• How to stall the pipeline at ID stage? add
  hazard detection unit
• Set all control signals to 0, inserting a bubble
  (NOP operation)
• Keep IF/ID unchanged repeat the previous cycle
• Keep PC unchanged refetch the same instruction
• Add PCWrite and IF/IDWrite control to to data
  hazard detection logic
• What is the difference between the hazard
  detection unit and data forwarding unit?

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Pipelined Control with Hazard Detection and Data
Forwarding Units
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Example Clock 2
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Clock 3
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Clock 4
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Clock 5
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Clock 6
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Clock 7
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Questions?