Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits

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Automated Design of Misaligned-Carbon-Nanotube-Im
mune Circuits

• Nishant Patil
• Jie Deng
• H.-S. Philip Wong
• Subhasish Mitra
• Departments of Electrical Engineering Computer
  Science
• Stanford University

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Misaligned Carbon Nanotubes (CNTs)
Aligned CNTs on Quartz Prof. Zhou, USC

• Misaligned-CNT-Immune Logic Design

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CNFET Transistor Layout
Lithographic Gate
Oxide
CNT doped region
CNT undoped region
Substrate (e.g Quartz)
CNT undoped region
Side View
Top View
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Perfect CNFET Inverter Layout
Vdd Contact
P doped Semiconducting CNTs
64nm 4?
Input
4nm
Output Contact
Gate
Input
V. Derycke et al., Nano Letters, p. 453, 2001.
N doped Semiconducting CNTs
Gnd Contact
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CNFET Fabrication Process

• Define cell regions
• on substrate
• Etch CNTs outside
• cell regions
• Define gates and contacts
• Chemically dope CNTs

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CNFET Imperfections Misaligned CNTs
Vdd
Vdd
Vdd
A
Short
Gate A
B
A
B
Out
A
Gate B
B
C
D
Out
Gnd
Gnd
Out
Gate A
Wanted AC BD Got AC BD AD
Gate B
Gnd
Wanted AB in pullup Got Short
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Misaligned-CNT-Immune NAND Design

• Grow CNTs
• Define gates and contacts
• Chemically dope P-type region
• Chemically dope N-type region
• Etch

Undoped region enables misaligned-CNT-immune
design
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Misaligned-CNT-Immune NAND Design

• Grow CNTs
• Define gates and contacts
• Etch CNTs
• Chemically dope P-type region
• Chemically dope N-type region

Etched region enables misaligned-CNT-immune design
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Generalized Algorithm

• Characterize Layout
• Misaligned-CNT-Immune
• OR
• Misaligned-CNT-Vulnerable
• Implement Arbitrary Logic function
• Misaligned-CNT-Immune Layout

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Misaligned-CNT-Vulnerable NAND Pull-up
Intended Function A or B
C
C
C
Contact
D
D
D
GA
A
GA
D
Doped
D
D
D
GB
B
GB
D
Gate A
D
D
D
Gate B
C
C
C
Contact
Implemented Function A or B or (A AND B) or 1
1 ! A or B
Path 1 C-D-A-D-C fn A Path 2 C-D-B-D-C fn
B Path 3 C-D-A-D-B-D-C fn A B Path 4
C-D-C fn 1
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Misaligned-CNT-Immune NAND Pull-up
Path 1 C-D-A-D-C fn A Path 2 C-D-B-D-C fn
B Path 3 C-D-A-D-B-C fn A B Path 4
C-D-B-UD-A-D-C fn 0
Contact
Doped
UD
GA
GB
Doped
Contact
Contact
Intended Function A or B Implemented Function A
or B or (A and B) or (A and B and 0) A or B
Doped
Undoped
Gate B
Gate A
Doped
Contact
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Misaligned-CNT-Immune Arbitrary Function
A (B C)(D E)
Undoped regions
Vdd/ Gnd Contact
CNTs
C
B
A
Gates
Intermediate Contact
D
E
Output Contact

• Immune to ANY number of misaligned CNTs
• Arbitrary logic function
• Formal correctness proof (Details in paper)

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Simulation Results

• Misaligned-CNT-Immune vs. Misaligned-CNT-Vulnerabl
  e
• CNFET model ? Deng Wong, SISPAD 06
• 10 accuracy DC AC measurements
• Amlani, et al., IEDM 06

Penalties over Vulnerable CNFET Circuit Penalties over Vulnerable CNFET Circuit Penalties over Vulnerable CNFET Circuit
Cell Type Area Energy Delay max rise, fall
nand2 -1 3 -7
nand3 11 15 10
nor2 -1 5 1
nor3 11 16 10
aoi21 -2 1 1
Full Adder 12 10 7
Significantly less penalty vs. traditional fault
tolerance
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Conclusion

• Misaligned CNT Immune Design
• Perfect alignment not needed immune by design
• Ideal case 13X better EDP vs. 32nm CMOS
• Efficient misaligned-CNT-immune circuits
• Significantly less overhead than replication
• Metallic CNTs

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Thank You
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Misaligned-CNT-Vulnerable NAND Pulldown
Intended Function A and B Path
C-D-A-D-B-D-C Implemented Function A and B
Contact
Doped
A
Gate A
Doped
B
Gate B
Doped
Contact