Diploma Project

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Diploma Project

• Real Time Motion Estimation on HDTV Video Streams
  
• (using the Xilinx FPGA)

Supervisor Averena L.I.Student Das Samarjit
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Introduction

• In this project I estimate the motion on HDTV
  video stream using the fastest motion estimation
  Algorithm with the FPGA of Xilinx Technology.
• I also implemented the motion estimation
  Algorithm to compensate the video frame to
  achieve better quality with lowest power
  consumption and flexible platform.
• Finally I generated the VHDL code for the Data
  processing unit for it to be implemented inside
  the FPGA architecture to obtain optimum
  performance.

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Motion Estimation Algorithm

• Frame differencing method.
• Vector quantization method

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Hybrid Video Encoding

• Simplified MPEG-1 Encoder

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Hybrid Video Decoding

• Simplified MPEG-1 Decoder

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Motion Estimation(Dominant Algorithm)
Computational Power Distribution (for HDTV Tools)
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Principals of Block Matching Motion Estimation
Block Matching Algorithm
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Block Matching Process-i
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Block Matching Process-ii
Block Matching Algorithm
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Classification of Motion Estimation

• Gradient Based Motion Estimation(For Image
  sequence analysis).
• Pel-Recursive Motion Estimation(For Image
  Sequence coding).
• Block Matching Motion estimation(Best used for
  Video frame sequence coding).
• Frequency Domain Motion estimation (For video
  Encryption)

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The Search Algorithm
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The Tree step search Algorithm
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The 2-D Logarithmic search Algorithm
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Hexagonal Based search Algorithm
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Motion Estimation Process in H.264/AVC

• A Fast Integer Pel search to estimate the motion
  vector.
• A fractional pel search to determine the motion
  vector to a higher accuracy.

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Block Diagram of H.264/AVC encoder
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Motion Compensation with small block size
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¼ Pixel accurate motion compensation
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Multiple Reference Picture motion compensation
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Review of reconfigurable array architecture
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The Reconfigurable instruction cell array
architecture (RICA)
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Design Flow for Algorithm implimentation on (RICA)
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Flex WAFE Architecture with FIR Filter DPU

• Data stream communicators component (LMCs).
• Data stream processor component (DPUs).
• Image Algorithm Dependent Global control (AC).

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Flex WAFE Architecture with FIR Filter DPU
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Flex WAFE Architecture building block

• LMC (here data is transferred reorganised and
  stored ).
• DPU (It processes the data stream provided by the
  LMC).
• AC (It reacts to the DPU and LMC via point to
  point connection to control the algorithm.

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Comparison between DCT and DWT.
Performance comparison of ZTE Wavelet coder
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Compression Performance with respect of human
visual system HVS
A
B
c
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Test image ROI encoding
A test image used to demonstrate the advantages
of ROI coding
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Implementation to FPGA
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Compairing resources of a FPGA used DCT
DWT.(a) Xilinx virtex E-Series(b) Alteras Apex
20KE series
(a)
(b)
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Implimentation of Fast DCTIDCT algorithm using
various FPGA
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Implementation on Xilinx FPGA
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Performance of Xilinx FPGA
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Overall Result

• Observing the result graph we depict that only
  Xilinxs FPGA is able to process twice the rate
  required by the HDTV video stream which is a
  remarkable achievement.
• By implementing a very fast DCT algorithm in
  Xilinx FPGA, I am able to process HDTV frames at
  a higher rate
• So by implementing a very fast DCT algorithm
  (using the selected xilinx FPGA) I encrypt
  therefore encode the static image of video frame
  and then I implement the motion estimation
  algorithm to compensate the video frame to
  achieve better quality with lowest power
  consumption and time therefore estimate the
  motion estimation on HDTV video streams in the
  real time using the Xilinx FPGA technology.